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this is information on a product in full production. september 2013 doc id 16100 rev 7 1/103 1 spc560p34l1, spc560p34l3 SPC560P40L1, spc560p40l3 32-bit power architecture ? based mcu with 320 kb flash memory and 20 kb ram for automotive chassis and safety applications datasheet ? production data features up to 64 mhz, single issue, 32-bit cpu core complex (e200z0h) ? compliant with power architecture ? embedded category ? variable length encoding (vle) memory organization ? up to 256 kb on-chip code flash memory with ecc and erase/program controller ? additional 64 (4 16) kb on-chip data flash memory with ecc for eeprom emulation ? up to 20 kb on-chip sram with ecc fail-safe protection ? programmable watchdog timer ? non-maskable interrupt ? fault collection unit nexus class 1 interface interrupts and events ? 16-channel edma controller ? 16 priority level controller ? up to 25 external interrupts ? pit implements four 32-bit timers ? 120 interrupts are routed via intc general purpose i/os ? individually programmable as input, output or special function ? 37 on lqfp64 ? 64 on lqfp100 1 general purpose etimer unit ? 6 timers each with up/down capabilities ? 16-bit resolution, cascadable counters ? quadrature decode with rotation direction flag ? double buffer input capture and output compare communications interfaces ? 2 linflex channels (1 master/slave, 1 master only) ? up to 3 dspi channels with automatic chip select generation (up to 8/4/4 chip selects) ? up to 2 flexcan interface (2.0b active) with 32 message buffers ? 1 safety port based on flexcan with 32 message buffers and up to 8 mbit/s at 64 mhz capability usable as second can when not used as safety port one 10-bit analog-to-digital converter (adc) ? up to 16 input channels (16 on lqfp100 / 12 on lqfp64) ? conversion time < 1 s including sampling time at full precision ? programmable cross triggering unit (ctu) ? 4 analog watchdogs with interrupt capability on-chip can/uart bootstrap loader with boot assist module (bam) 1 flexpwm unit: 8 complementary or independent outputs with adc synchronization signals table 1. device summary package code flash memory 192 kb 256 kb lqfp100 spc560p34l3 spc560p40l3 lqfp64 spc560p34l1 SPC560P40L1 lqfp64 (10 x 10 x 1.4 mm) lqfp100 (14 x 14 x 1.4 mm) www.st.com
contents spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 2/103 doc id 16100 rev 7 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3 device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.5 feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.5.1 high performance e200z0 core processor . . . . . . . . . . . . . . . . . . . . . . . 13 1.5.2 crossbar switch (xbar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.5.3 enhanced direct memory access (edma) . . . . . . . . . . . . . . . . . . . . . . . 14 1.5.4 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.5.5 static random access memory (sram) . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.5.6 interrupt controller (intc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.5.7 system status and configuration module (sscm) . . . . . . . . . . . . . . . . . 16 1.5.8 system clocks and clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.5.9 frequency-modulated phase-locked loop (fmpll) . . . . . . . . . . . . . . . . 17 1.5.10 main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.5.11 internal rc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.5.12 periodic interrupt timer (pit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.5.13 system timer module (stm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.5.14 software watchdog timer (swt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.5.15 fault collection unit (fcu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.5.16 system integration unit ? lite (siul) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.5.17 boot and censorship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.5.18 error correction status module (ecsm) . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.5.19 peripheral bridge (pbridge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.5.20 controller area network (flexcan) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.5.21 safety port (flexcan) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.5.22 serial communication interface module (linflex) . . . . . . . . . . . . . . . . . 22 1.5.23 deserial serial peripheral interface (dspi) . . . . . . . . . . . . . . . . . . . . . . 23 1.5.24 pulse width modulator (flexpwm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.5.25 etimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.5.26 analog-to-digital converter (adc) module . . . . . . . . . . . . . . . . . . . . . . . 25 1.5.27 cross triggering unit (ctu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5.28 nexus development interface (ndi) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 contents doc id 16100 rev 7 3/103 1.5.29 cyclic redundancy check (crc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.30 ieee 1149.1 jtag controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.31 on-chip voltage regulator (vreg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2 package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 29 2.1 package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.2.1 power supply and reference voltage pins . . . . . . . . . . . . . . . . . . . . . . . 33 2.2.2 system pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.2.3 pin multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.2 parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.4 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.5.1 package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.5.2 general notes for specifications at maximum junction temperature . . . 52 3.6 electromagnetic interference (emi) characteristics . . . . . . . . . . . . . . . . . 54 3.7 electrostatic discharge (esd) characteristics . . . . . . . . . . . . . . . . . . . . . 54 3.8 power management electrical characteristics . . . . . . . . . . . . . . . . . . . . . 54 3.8.1 voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 54 3.8.2 voltage monitor electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 57 3.9 power up/down sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.10 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.10.1 nvusro register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.10.2 dc electrical characteristics (5 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.10.3 dc electrical characteristics (3.3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.10.4 input dc electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . 63 3.10.5 i/o pad current specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.11 main oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.12 fmpll electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.13 16 mhz rc oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . 68 3.14 analog-to-digital converter (adc) electrical characteristics . . . . . . . . . . . 68
contents spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 4/103 doc id 16100 rev 7 3.14.1 input impedance and adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 3.14.2 adc conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.15 flash memory electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.15.1 program/erase characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.15.2 flash memory power supply dc characteristics . . . . . . . . . . . . . . . . . . 75 3.15.3 start-up/switch-off timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 3.16 ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 3.16.1 pad ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 3.17 ac timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.17.1 reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.17.2 ieee 1149.1 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 3.17.3 nexus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 3.17.4 external interrupt timing (irq pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 3.17.5 dspi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 4.1 ecopack? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 4.2 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 4.2.1 lqfp100 mechanical outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . 92 4.2.2 lqfp64 mechanical outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 5 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 appendix a abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 list of tables doc id 16100 rev 7 5/103 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. spc560p34/spc560p40 device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. spc560p40 device configuration differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 4. spc560p34/spc560p40 series block summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 5. supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 6. system pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 7. pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 8. parameter classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 9. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 10. recommended operating conditions (5.0 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 11. recommended operating conditions (3.3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 12. lqfp thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 13. emi testing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 14. esd ratings, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 15. approved npn ballast components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 16. voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 17. low voltage monitor electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 18. pad3v5v field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 19. dc electrical characteristics (5.0 v, nvusro[pad3v5v] = 0) . . . . . . . . . . . . . . . . . . . . . 60 table 20. supply current (5.0 v, nvusro[pad3v5v] = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 21. dc electrical characteristics (3.3 v, nvusro[pad3v5v] = 1) . . . . . . . . . . . . . . . . . . . . . 62 table 22. supply current (3.3 v, nvusro[pad3v5v] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 23. i/o supply segment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 24. i/o consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 25. main oscillator output electrical characteristics (5.0 v, nvusro[pad3v5v] = 0) . . . . . . . 65 table 26. main oscillator output electrical characteristics (3.3 v, nvusro[pad3v5v] = 1) . . . . . . . 66 table 27. input clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 28. fmpll electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 29. 16 mhz rc oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 30. adc conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 31. program and erase specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 32. flash memory module life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 33. flash memory read access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 34. flash memory power supply dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 35. start-up time/switch-off time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 36. output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 37. reset electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 38. jtag pin ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 39. nexus debug port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 40. external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 41. dspi timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 42. lqfp100 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 43. lqfp64 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 44. abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 45. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
list of figures spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 6/103 doc id 16100 rev 7 list of figures figure 1. block diagram (spc560p40 full-featured configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 2. 64-pin lqfp pinout ? full featured configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . 29 figure 3. 64-pin lqfp pinout ? airbag configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 4. 100-pin lqfp pinout ? full featured configuration (top view) . . . . . . . . . . . . . . . . . . . . . . 31 figure 5. 100-pin lqfp pinout ? airbag configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 6. power supplies constraints (?0.3 v v dd_hv_iox 6.0 v). . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 7. independent adc supply (?0.3 v v dd_hv_reg 6.0 v) . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 8. power supplies constraints (3.0 v v dd_hv_iox 5.5 v). . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 9. independent adc supply (3.0 v v dd_hv_reg 5.5 v) . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 10. voltage regulator configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 11. power-up typical sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 12. power-down typical sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 13. brown-out typical sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 14. input dc electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 15. adc characteristics and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 16. input equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 17. transient behavior during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 18. spectral representation of input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 19. pad output delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 20. start-up reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 21. noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 22. jtag test clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 23. jtag test access port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 24. jtag boundary scan timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 25. nexus output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 26. nexus event trigger and test clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 27. nexus tdi, tms, tdo timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 28. external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 29. dspi classic spi timing ? master, cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 30. dspi classic spi timing ? master, cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 31. dspi classic spi timing ? slave, cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 32. dspi classic spi timing ? slave, cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 33. dspi modified transfer format timing ? master, cpha = 0. . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 34. dspi modified transfer format timing ? master, cpha = 1. . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 35. dspi modified transfer format timing ? slave, cpha = 0. . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 36. dspi modified transfer format timing ? slave, cpha = 1. . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 37. dspi pcs strobe (pcss) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 38. lqfp100 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 39. lqfp64 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 40. commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 introduction doc id 16100 rev 7 7/103 1 introduction 1.1 document overview this document provides electrical specifications, pin assignments, and package diagrams for the spc560p34/40 series of microcontroller units (mcus). it also describes the device features and highlights important electrical and physical characteristics. for functional characteristics, refer to the device reference manual. 1.2 description this 32-bit system-on-chip (soc) automotive microcontroller family is the latest achievement in integrated automotive application controllers. it belongs to an expanding range of automotive-focused products designed to address chassis applications? specifically, electrical hydraulic power steering (ehps) and electric power steering (eps)? as well as airbag applications. this family is one of a series of next-generation integrated automotive microcontrollers based on the power architecture technology. the advanced and cost-efficient host processor core of this automotive controller family complies with the power architecture embedded category. it operates at speeds of up to 64 mhz and offers high performance processing optimized for low power consumption. it capitalizes on the available development infrastructure of current power architecture devices and is supported with software drivers, operating systems and configuration code to assist with users implementations. 1.3 device comparison ta ble 2 provides a summary of different members of the spc560p34/spc560p40 family and their features?relative to full-featured version?to enable a comparison among the family members and an understanding of the range of functionality offered within this family. table 2. spc560p34/spc560p40 device comparison feature spc560p34 full-featured spc560p40 full-featured code flash memory (with ecc) 192 kb 256 kb data flash memory / ee option (with ecc) 64 kb sram (with ecc) 12 kb 20 kb processor core 32-bit e200z0h instruction set vle (variable length encoding) cpu performance 0?64 mhz fmpll (frequency-modulated phase-locked loop) module 1 intc (interrupt controller) channels 120 pit (periodic interrupt timer) 1 (with four 32-bit timers)
introduction spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 8/103 doc id 16100 rev 7 spc560p34/spc560p40 is available in two configurations having different features: full- featured and airbag. tab le 3 shows the main differences between the two versions of the spc560p40 mcu. edma (enhanced direct memory access) channels 16 flexcan (controller area network) 1 (1) 2 (1),(2) safety port no yes (via second flexcan module) fcu (fault collection unit) yes ctu (cross triggering unit) yes yes etimer 1 (16-bit, 6 channels) flexpwm (pulse-width modulation) channels 8 (capture capabity not supported) 8 (capture capability not supported) analog-to-digital converter (adc) 1 (10-bit, 16 channels) linflex 2 (1 master/slave, 1 master only) 2 (1 master/slave, 1 master only) dspi (deserial serial peripheral interface) 2 3 crc (cyclic redundancy check) unit yes junction temperature sensor no jtag controller yes nexus port controller (npc) yes (nexus class 1) supply digital power supply (3) 3.3 v or 5 v single supply with external transistor analog power supply 3.3 v or 5 v internal rc oscillator 16 mhz external crystal oscillator 4?40 mhz packages lqfp64 lqfp100 temperature standard ambient temperature ?40 to 125 c 1. each flexcan module has 32 message buffers. 2. one flexcan module can act as a safety port with a bit rate as high as 8 mbit/s at 64 mhz. 3. the different supply voltages vary according to the part number ordered. table 2. spc560p34/spc560p40 device comparison (continued) feature spc560p34 full-featured spc560p40 full-featured
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 introduction doc id 16100 rev 7 9/103 1.4 block diagram figure 1 shows a top-level block diagram of the spc560p34/spc560p40 mcu. table 2 summarizes the functions of the blocks. table 3. spc560p40 device configuration differences feature configuration airbag full-featured sram (with ecc) 16 kb 20 kb flexcan (controller area network) 1 2 safety port no yes (via second flexcan module) flexpwm (pulse-width modulation) channels no 8 (capture capability not supported) ctu (cross triggering unit) no yes
introduction spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 10/103 doc id 16100 rev 7 figure 1. block diagram (spc560p4 0 full-featured configuration) sram (with ecc) slave slave slave code flash (with ecc) data flash (with ecc) pit stm swt mc_rgm mc_cgm mc_me bam siul wkpu crc ecsm e200z0 core 32-bit general purpose registers special purpose registers integer execution unit exception handler variable length encoded instructions instruction unit load/store unit branch prediction unit jtag 1.2 v regulator control xosc 16 mhz rc oscillator fmpll_0 (system) nexus port controller interrupt controller edma 16 channels master master instruction 32-bit master data 32-bit crossbar switch (xbar, amba 2.0 v6 ahb) peripheral bridge fcu legend: adc analog-to-digital converter bam boot assist module crc cyclic redundancy check ctu cross triggering unit dspi deserial serial peripheral interface ecsm error correction status module edma enhanced direct memory access etimer enhanced timer fcu fault collection unit flash flash memory flexcan controller area network flexpwm flexible pulse width modulation fmpll frequency-modulated phase-locked loop intc interrupt controller jtag jtag controller linflex serial communication interface (lin support) mc_cgm clock generation module mc_me mode entry module mc_pcu power control unit mc_rgm reset generation module pit periodic interrupt timer siul system integration unit lite sram static random-access memory sscm system status and configuration module stm system timer module swt software watchdog timer wkpu wakeup unit xosc external oscillator xbar crossbar switch external ballast nexus 1 edma 16 channels flexpwm ctu 3 etimer dspi 2 flexcan linflex safety port adc (6 ch) sscm (10 bit, 16 ch)
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 introduction doc id 16100 rev 7 11/103 table 4. spc560p34/spc560p40 series block summary block function analog-to-digital converter (adc) multi-channel, 10-bit analog-to-digital converter boot assist module (bam) block of read-only memory containing vle code which is executed according to the boot mode of the device clock generation module (mc_cgm) provides logic and control required for the generation of system and peripheral clocks controller area network (flexcan) supports the standard can communications protocol cross triggering unit (ctu) enables synchronization of adc conversions with a timer event from the emios or from the pit crossbar switch (xbar) supports simultaneous connections between two master ports and three slave ports; supports a 32-bit address bus width and a 32-bit data bus width cyclic redundancy check (crc) crc checksum generator deserial serial peripheral interface (dspi) provides a synchronous serial interface for communication with external devices enhanced direct memory access (edma) performs complex data transfers with minimal intervention from a host processor via ? n ? programmable channels enhanced timer (etimer) provides enhanced programmable up/down modulo counting error correction status module (ecsm) provides a myriad of miscellaneous control functions for the device including program-visible information about configuration and revision levels, a reset status register, wakeup control for exiting sleep modes, and optional features such as information on memory errors reported by error-correcting codes external oscillator (xosc) provides an output clock used as input reference for fmpll_0 or as reference clock for specific modules depending on system needs fault collection unit (fcu) provides functional safety to the device flash memory provides non-volatile storage for program code, constants and variables frequency-modulated phase- locked loop (fmpll) generates high-speed system clocks and supports programmable frequency modulation interrupt controller (intc) provides priority-based preemptive scheduling of interrupt requests jtag controller provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode linflex controller manages a high number of lin (local interconnect network protocol) messages efficiently with a minimum of cpu load mode entry module (mc_me) provides a mechanism for controlling the device operational mode and mode transition sequences in all functional states; also manages the power control unit, reset generation module and clock generation module, and holds the configuration, control and status registers accessible for applications periodic interrupt timer (pit) produces periodic interrupts and triggers peripheral bridge (pbridge) is the interface between the system bus and on-chip peripherals power control unit (mc_pcu) reduces the overall power consumption by disconnecting parts of the device from the power supply via a power switching device; device components are grouped into sections called ?power domains? which are controlled by the pcu
introduction spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 12/103 doc id 16100 rev 7 pulse width modulator (flexpwm) contains four pwm submodules, each of which capable of controlling a single half-bridge power stage and two fault input channels reset generation module (mc_rgm) centralizes reset sources and manages the device reset sequence of the device static random-access memory (sram) provides storage for program code, constants, and variables system integration unit lite (siul) provides control over all the electrical pad controls and up 32 ports with 16 bits of bidirectional, general-purpose input and output signals and supports up to 32 external interrupts with trigger event configuration system status and configuration module (sscm) provides system configuration and status data (such as memory size and status, device mode and security status), device identification data, debug status port enable and selection, and bus and peripheral abort enable/disable system timer module (stm) provides a set of output compare events to support autosar (1) and operating system tasks system watchdog timer (swt) provides protection from runaway code wakeup unit (wkpu) supports up to 18 external sources that can generate interrupts or wakeup events, of which 1 can cause non-maskable interrupt requests or wakeup events 1. autosar: automotive open system architecture (see www.autosar.org) table 4. spc560p34/spc560p40 series block summary (continued) block function
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 introduction doc id 16100 rev 7 13/103 1.5 feature details 1.5.1 high performance e200z0 core processor the e200z0 power architecture core provides the following features: high performance e200z0 core processor for managing peripherals and interrupts single issue 4-stage pipeline in-order execution 32-bit power architecture cpu harvard architecture variable length encoding (vle), allowing mixed 16- and 32-bit instructions ? results in smaller code size footprint ? minimizes impact on performance branch processing acceleration using lookahead instruction buffer load/store unit ? 1-cycle load latency ? misaligned access support ? no load-to-use pipeline bubbles thirty-two 32-bit general purpose registers (gprs) separate instruction bus and load/store bus harvard architecture hardware vectored interrupt support reservation instructions for implementing read-modify-write constructs long cycle time instructions, except for guarded loads, do not increase interrupt latency extensive system development support through nexus debug port non-maskable interrupt support 1.5.2 crossbar switch (xbar) the xbar multi-port crossbar switch supports simultaneous connections between three master ports and three slave ports. the crossbar supports a 32-bit address bus width and a 32-bit data bus width. the crossbar allows for two concurrent transactions to occur from any master port to any slave port; but one of those transfers must be an instruction fetch from internal flash memory. if a slave port is simultaneously requested by more than one master port, arbitration logic will select the higher priority master and grant it ownership of the slave port. all other masters requesting that slave port will be stalled until the higher priority master completes its transactions. requesting masters will be treated with equal priority and will be granted access a slave port in round-robin fashion, based upon the id of the last master to be granted access.
introduction spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 14/103 doc id 16100 rev 7 the crossbar provides the following features: 3 master ports: ? e200z0 core complex instruction port ? e200z0 core complex load/store data port ?edma 3 slave ports: ? flash memory (code and data) ?sram ? peripheral bridge 32-bit internal address, 32-bit internal data paths fixed priority arbitration based on port master temporary dynamic priority elevation of masters 1.5.3 enhanced direct memory access (edma) the enhanced direct memory access (edma) controller is a second-generation module capable of performing complex data movements via 16 programmable channels, with minimal intervention from the host processor. the hardware micro architecture includes a dma engine which performs source and destination address calculations, and the actual data movement operations, along with an sram-based memory containing the transfer control descriptors (tcd) for the channels. the edma module provides the following features: 16 channels support independent 8-, 16- or 32-bit single value or block transfers supports variable-sized queues and circular queues source and destination address registers are independently configured to either post- increment or to remain constant each transfer is initiated by a peripheral, cpu, or edma channel request each edma channel can optionally send an interrupt request to the cpu on completion of a single value or block transfer dma transfers possible between system memories, dspis, adc, flexpwm, etimer and ctu programmable dma channel multiplexer allows assignment of any dma source to any available dma channel with as many as 30 request sources edma abort operation through software 1.5.4 flash memory the spc560p34/spc560p40 provides 320 kb of programmable, non-volatile, flash memory. the non-volatile memory (nvm) can be used for instruction and/or data storage. the flash memory module is interfaced to the system bus by a dedicated flash memory controller. it supports a 32-bit data bus width at the system bus port, and a 128-bit read data interface to flash memory. the module contains four 128-bit wide prefetch buffers. prefetch buffer hits allow no-wait responses. normal flash memory array accesses are registered and are forwarded to the system bus on the following cycle, incurring two wait-states.
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 introduction doc id 16100 rev 7 15/103 the flash memory module provides the following features: as much as 320 kb flash memory ? 6 blocks (32 kb + 216 kb + 32 kb + 32 kb + 128 kb) code flash memory ? 4 blocks (16 kb + 16 kb + 16 kb + 16 kb) data flash memory ? full read-while-write (rww) capability between code flash memory and data flash memory four 128-bit wide prefetch buffers to provide single cycle in-line accesses (prefetch buffers can be configured to prefetch code or data or both) typical flash memory access time: no wait-state for buffer hits, 2 wait-states for page buffer miss at 64 mhz hardware managed flash memory writes handled by 32-bit risc krypton engine hardware and software configurable read and write access protections on a per-master basis configurable access timing allowing use in a wide range of system frequencies multiple-mapping support and mapping-based block access timing (up to 31 additional cycles) allowing use for emulation of other memory types software programmable block program/erase restriction control erase of selected block(s) read page sizes ? code flash memory: 128 bits (4 words) ? data flash memory: 32 bits (1 word) ecc with single-bit correction, double-bit detection for data integrity ? code flash memory: 64-bit ecc ? data flash memory: 32-bit ecc embedded hardware program and erase algorithm erase suspend and program abort censorship protection scheme to prevent flash memory content visibility hardware support for eeprom emulation 1.5.5 static random access memory (sram) the spc560p34/spc560p40 sram module provides up to 20 kb of general-purpose memory. the sram module provides the following features: supports read/write accesses mapped to the sram from any master up to 20 kb general purpose sram supports byte (8-bit), half word (16-bit), and word (32-bit) writes for optimal use of memory typical sram access time: no wait-state for reads and 32-bit writes; 1 wait-state for 8- and 16-bit writes if back-to-back with a read to same memory block
introduction spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 16/103 doc id 16100 rev 7 1.5.6 interrupt controller (intc) the interrupt controller (intc) provides priority-based preemptive scheduling of interrupt requests, suitable for statically scheduled hard real-time systems. the intc handles 128 selectable-priority interrupt sources. for high-priority interrupt requests, the time from the assertion of the interrupt request by the peripheral to the execution of the interrupt service routine (isr) by the processor has been minimized. the intc provides a unique vector for each interrupt request source for quick determination of which isr has to be executed. it also provides a wide number of priorities so that lower priority isrs do not delay the execution of higher priority isrs. to allow the appropriate priorities for each source of interrupt request, the priority of each interrupt request is software configurable. when multiple tasks share a resource, coherent accesses to that resource need to be supported. the intc supports the priority ceiling protocol (pcp) for coherent accesses. by providing a modifiable priority mask, the priority can be raised temporarily so that all tasks which share the same resource can not preempt each other. the intc provides the following features: unique 9-bit vector for each separate interrupt source 8 software triggerable interrupt sources 16 priority levels with fixed hardware arbitration within priority levels for each interrupt source ability to modify the isr or task priority: modifying the priority can be used to implement the priority ceiling protocol for accessing shared resources. 1 external high priority interrupt (nmi) directly accessing the main core and i/o processor (iop) critical interrupt mechanism 1.5.7 system status and configuration module (sscm) the system status and configuration module (sscm) provides central device functionality. the sscm includes these features: system configuration and status ? memory sizes/status ? device mode and security status ? determine boot vector ? search code flash for bootable sector ?dma status debug status port enable and selection bus and peripheral abort enable/disable
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 introduction doc id 16100 rev 7 17/103 1.5.8 system clocks and clock generation the following list summarizes the system clock and clock generation on the spc560p34/spc560p40: lock detect circuitry continuously monitors lock status loss of clock (loc) detection for pll outputs programmable output clock divider ( 1, 2, 4, 8) flexpwm module and etimer module running at the same frequency as the e200z0h core internal 16 mhz rc oscillator for rapid start-up and safe mode: supports frequency trimming by user application 1.5.9 frequency-modulated phase-locked loop (fmpll) the fmpll allows the user to generate high speed system clocks from a 4?40 mhz input clock. further, the fmpll supports programmable frequency modulation of the system clock. the pll multiplication factor, output clock divider ratio are all software configurable. the fmpll has the following major features: input clock frequency: 4?40 mhz maximum output frequency: 64 mhz voltage controlled oscillator (vco)?frequency 256?512 mhz reduced frequency divider (rfd) for reduced frequency operation without forcing the fmpll to relock frequency-modulated pll ? modulation enabled/disabled through software ? triangle wave modulation programmable modulation depth (0.25% to 4% deviation from center frequency): programmable modulation frequency dependent on reference frequency self-clocked mode (scm) operation 1.5.10 main oscillator the main oscillator provides these features: input frequency range: 4?40 mhz crystal input mode or oscillator input mode pll reference 1.5.11 internal rc oscillator this device has an rc ladder phase-shift oscillator. the architecture uses constant current charging of a capacitor. the voltage at the capacitor is compared by the stable bandgap reference voltage.
introduction spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 18/103 doc id 16100 rev 7 the rc oscillator provides these features: nominal frequency 16 mhz 5% variation over voltage and temperature after process trim clock output of the rc oscillator serves as system clock source in case loss of lock or loss of clock is detected by the pll rc oscillator is used as the default system clock during startup 1.5.12 periodic interrupt timer (pit) the pit module implements these features: 4 general-purpose interrupt timers 32-bit counter resolution clocked by system clock frequency each channel usable as trigger for a dma request 1.5.13 system timer module (stm) the stm implements these features: one 32-bit up counter with 8-bit prescaler four 32-bit compare channels independent interrupt source for each channel counter can be stopped in debug mode 1.5.14 software watchdog timer (swt) the swt has the following features: 32-bit time-out register to set the time-out period programmable selection of window mode or regular servicing programmable selection of reset or interrupt on an initial time-out master access protection hard and soft configuration lock bits reset configuration inputs allow timer to be enabled out of reset 1.5.15 fault collection unit (fcu) the fcu provides an independent fault reporting mechanism even if the cpu is malfunctioning. the fcu module has the following features: fcu status register reporting the device status continuous monitoring of critical fault signals user selection of critical signals from different fault sources inside the device critical fault events trigger 2 external pins (user selected signal protocol) that can be used externally to reset the device and/or other circuitry (for example, a safety relay) faults are latched into a register
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 introduction doc id 16100 rev 7 19/103 1.5.16 system integration unit ? lite (siul) the spc560p34/spc560p40 siul controls mcu pad configuration, external interrupt, general purpose i/o (gpio), and internal peripheral multiplexing. the pad configuration block controls the static electrical characteristics of i/o pins. the gpio block provides uniform and discrete input/output control of the i/o pins of the mcu. the siul provides the following features: centralized general purpose input output (gpio) control of up to 49 input/output pins and 16 analog input-only pads (package dependent) all gpio pins can be independently configured to support pull-up, pull-down, or no pull reading and writing to gpio supported both as individual pins and 16-bit wide ports all peripheral pins, except adc channels, can be alternatively configured as both general purpose input or output pins adc channels support alternative configuration as general purpose inputs direct readback of the pin value is supported on all pins through the siul configurable digital input filter that can be applied to some general purpose input pins for noise elimination up to 4 internal functions can be multiplexed onto 1 pin 1.5.17 boot and censorship different booting modes are available in the spc560p34/spc560p40: booting from internal flash memory and booting via a serial link. the default booting scheme uses the internal flash memory (an internal pull-down resistor is used to select this mode). optionally, the user can boot via flexcan or linflex (using the boot assist module software). a censorship scheme is provided to protect the content of the flash memory and offer increased security for the entire device. a password mechanism is designed to grant the legitimate user access to the non-volatile memory. boot assist module (bam) the bam is a block of read-only memory that is programmed once and is identical for all spc560pxx devices that are based on the e200z0h core. the bam program is executed every time the device is powered on if the alternate boot mode has been selected by the user. the bam provides the following features: serial bootloading via flexcan or linflex ability to accept a password via the used serial communication channel to grant the legitimate user access to the non-volatile memory 1.5.18 error correction status module (ecsm) the ecsm provides a myriad of miscellaneous control functions regarding program-visible information about the platform configuration and revision levels, a reset status register, a software watchdog timer, wakeup control for exiting sleep modes, and information on
introduction spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 20/103 doc id 16100 rev 7 platform memory errors reported by error-correcting codes and/or generic access error information for certain processor cores. the error correction status module supports a number of miscellaneous control functions for the platform. the ecsm includes these features: registers for capturing information on platform memory errors if error-correcting codes (ecc) are implemented for test purposes, optional registers to specify the generation of double-bit memory errors are enabled on the spc560p34/spc560p40. the sources of the ecc errors are: flash memory sram 1.5.19 peripheral bridge (pbridge) the pbridge implements the following features: duplicated periphery master access privilege level per peripheral (per master: read access enable; write access enable) write buffering for peripherals checker applied on pbridge output toward periphery byte endianess swap capability 1.5.20 controller area network (flexcan) the spc560p34/spc560p40 mcu contains one controller area network (flexcan) module. this module is a communication controller implementing the can protocol according to bosch specification version 2.0b. the can protocol was designed to be used primarily as a vehicle serial data bus, meeting the specific requirements of this field: real- time processing, reliable operation in the emi environment of a vehicle, cost-effectiveness and required bandwidth. the flexcan module contains 32 message buffers.
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 introduction doc id 16100 rev 7 21/103 the flexcan module provides the following features: full implementation of the can protocol specification, version 2.0b ? standard data and remote frames ? extended data and remote frames ? up to 8-bytes data length ? programmable bit rate up to 1 mbit/s 32 message buffers of up to 8-bytes data length each message buffer configurable as rx or tx, all supporting standard and extended messages programmable loop-back mode supporting self-test operation 3 programmable mask registers programmable transmit-first scheme: lowest id or lowest buffer number time stamp based on 16-bit free-running timer global network time, synchronized by a specific message maskable interrupts independent of the transmission medium (an external transceiver is assumed) high immunity to emi short latency time due to an arbitration scheme for high-priority messages transmit features ? supports configuration of multiple mailboxes to form message queues of scalable depth ? arbitration scheme according to message id or message buffer number ? internal arbitration to guarantee no inner or outer priority inversion ? transmit abort procedure and notification receive features ? individual programmable filters for each mailbox ? 8 mailboxes configurable as a 6-entry receive fifo ? 8 programmable acceptance filters for receive fifo programmable clock source ? system clock ? direct oscillator clock to avoid pll jitter 1.5.21 safety port (flexcan) the spc560p34/spc560p40 mcu has a second can controller synthesized to run at high bit rates to be used as a safety port. the can module of the safety port provides the following features: identical to the flexcan module bit rate up to 8 mbit/s at 64 mhz cpu clock using direct connection between can modules (no physical transceiver required) 32 message buffers of up to 8-bytes data length can be used as a second independent can module
introduction spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 22/103 doc id 16100 rev 7 1.5.22 serial communication interface module (linflex) the linflex (local interconnect network flexible) on the spc560p34/spc560p40 features the following: supports lin master mode (both instances), lin slave mode (only one instance) and uart mode lin state machine compliant to lin1.3, 2.0 and 2.1 specifications handles lin frame transmission and reception without cpu intervention lin features ? autonomous lin frame handling ? message buffer to store identifier and up to 8 data bytes ? supports message length of up to 64 bytes ? detection and flagging of lin errors (sync field, delimiter, id parity, bit framing, checksum, and time-out) ? classic or extended checksum calculation ? configurable break duration of up to 36-bit times ? programmable baud rate prescalers (13-bit mantissa, 4-bit fractional) ? diagnostic features: loop back; self test; lin bus stuck dominant detection ? interrupt-driven operation with 16 interrupt sources lin slave mode features: ? autonomous lin header handling ? autonomous lin response handling ? optional discarding of irrelevant lin responses using id filter uart mode: ? full-duplex operation ? standard non return-to-zero (nrz) mark/space format ? data buffers with 4-byte receive, 4-byte transmit ? configurable word length (8-bit or 9-bit words) ? error detection and flagging ? parity, noise and framing errors ? interrupt-driven operation with four interrupt sources ? separate transmitter and receiver cpu interrupt sources ? 16-bit programmable baud-rate modulus counter and 16-bit fractional ? 2 receiver wake-up methods
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 introduction doc id 16100 rev 7 23/103 1.5.23 deserial serial peripheral interface (dspi) the deserial serial peripheral interface (dspi) module provides a synchronous serial interface for communication between the spc560p34/spc560p40 mcu and external devices. the dspi modules provide these features: full duplex, synchronous transfers master or slave operation programmable master bit rates programmable clock polarity and phase end-of-transmission interrupt flag programmable transfer baud rate programmable data frames from 4 to 16 bits up to 8 chip select lines available: ?8 on dspi_0 ? 4 each on dspi_1 and dspi_2 8 clock and transfer attributes registers chip select strobe available as alternate function on one of the chip select pins for deglitching fifos for buffering up to 4 transfers on the transmit and receive side queueing operation possible through use of the i/o processor or edma general purpose i/o functionality on pins when not used for spi 1.5.24 pulse width modulator (flexpwm) the pulse width modulator module (pwm) contains four pwm submodules each of which is set up to control a single half-bridge power stage. there are also three fault channels. this pwm is capable of controlling most motor types: ac induction motors (acim), permanent magnet ac motors (pmac), both brushless (bldc) and brush dc motors (bdc), switched (srm) and variable reluctance motors (vrm), and stepper motors.
introduction spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 24/103 doc id 16100 rev 7 the flexpwm block implements the following features: 16-bit resolution for center, edge-aligned, and asymmetrical pwms clock frequency same as that used for e200z0h core pwm outputs can operate as complementary pairs or independent channels can accept signed numbers for pwm generation independent control of both edges of each pwm output synchronization to external hardware or other pwm supported double buffered pwm registers ? integral reload rates from 1 to 16 ? half cycle reload capability multiple adc trigger events can be generated per pwm cycle via hardware write protection for critical registers fault inputs can be assigned to control multiple pwm outputs programmable filters for fault inputs independently programmable pwm output polarity independent top and bottom deadtime insertion each complementary pair can operate with its own pwm frequency and deadtime values individual software-control for each pwm output all outputs can be programmed to change simultaneously via a ?force out? event pwmx pin can optionally output a third pwm signal from each submodule channels not used for pwm generation can be used for buffered output compare functions channels not used for pwm generation can be used for input capture functions enhanced dual-edge capture functionality edma support with automatic reload 2 fault inputs capture capability for pwma, pwmb, and pwmx channels not supported
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 introduction doc id 16100 rev 7 25/103 1.5.25 etimer the spc560p34/spc560p40 includes one etimer module which provides six 16-bit general purpose up/down timer/counter units with the following features: clock frequency same as that used for the e200z0h core individual channel capability ? input capture trigger ? output compare ? double buffer (to capture rising edge and falling edge) ? separate prescaler for each counter ? selectable clock source ? 0?100% pulse measurement ? rotation direction flag (quad decoder mode) maximum count rate ? external event counting: max. count rate = peripheral clock/2 ? internal clock counting: max. count rate = peripheral clock counters are: ? cascadable ? preloadable programmable count modulo quadrature decode capabilities counters can share available input pins count once or repeatedly pins available as gpio when timer functionality not in use 1.5.26 analog-to-digital converter (adc) module the adc module provides the following features: analog part: 1 on-chip analog-to-digital converter ? 10-bit ad resolution ? 1 sample and hold unit ? conversion time, including sampling time, less than 1 s (at full precision) ? typical sampling time is 150 ns minimum (at full precision) ? dnl/inl 1 lsb ?tue <1.5lsb ? single-ended input signal up to 3.3 v/5.0 v ? 3.3 v/5.0 v input reference voltage ? adc and its reference can be supplied with a voltage independent from v ddio ? adc supply can be equal or higher than v ddio ? adc supply and adc reference are not independent from each other (both internally bonded to same pad) ? sample times of 2 (default), 8, 64 or 128 adc clock cycles
introduction spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 26/103 doc id 16100 rev 7 digital part: 16 input channels 4 analog watchdogs comparing adc results against predefined levels (low, high, range) before results are stored in the appropriate adc result location 2 modes of operation: motor control mode or regular mode regular mode features ? register based interface with the cpu: control register, status register and 1 result register per channel ? adc state machine managing 3 request flows: regular command, hardware injected command and software injected command ? selectable priority between software and hardware injected commands ? dma compatible interface ctu-controlled mode features ? triggered mode only ? 4 independent result queues (116 entries, 28 entries, 14 entries) ? result alignment circuitry (left justified and right justified) ? 32-bit read mode allows to have channel id on one of the 16-bit part ? dma compatible interfaces 1.5.27 cross triggering unit (ctu) the cross triggering unit allows automatic generation of adc conversion requests on user selected conditions without cpu load during the pwm period and with minimized cpu load for dynamic configuration. it implements the following features: double buffered trigger generation unit with up to 8 independent triggers generated from external triggers trigger generation unit configurable in sequential mode or in triggered mode each trigger can be appropriately delayed to compensate the delay of external low pass filter double buffered global trigger unit allowing etimer synchronization and/or adc command generation double buffered adc command list pointers to minimize adc-trigger unit update double buffered adc conversion command list with up to 24 adc commands each trigger capable of generating consecutive commands adc conversion command allows to control adc channel, single or synchronous sampling, independent result queue selection 1.5.28 nexus development interface (ndi) the ndi (nexus development interface) block is compliant with nexus class 1 of the ieee- isto 5001-2003 standard. this development support is supplied for mcus without requiring external address and data pins for internal visibility. the ndi block is an integration of several individual nexus blocks that are selected to provide the development support interface for this device. the ndi block interfaces to the host processor and internal busses to provide development support as per the ieee-isto 5001-2003 nexus class 1 standard.
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 introduction doc id 16100 rev 7 27/103 the development support provided includes access to the mcu?s internal memory map and access to the processor?s internal registers. the ndi provides the following features: configured via the ieee 1149.1 all nexus port pins operate at v ddio (no dedicated power supply) nexus class 1 supports static debug 1.5.29 cyclic redundancy check (crc) the crc computing unit is dedicated to the computation of crc off-loading the cpu. the crc module features: support for crc-16-ccitt ( x 25 protocol): ? x 16 + x 12 + x 5 + 1 support for crc-32 (ethernet protocol): ? x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 zero wait states for each write/read operations to the crc_cfg and crc_inp registers at the maximum frequency 1.5.30 ieee 1149.1 jtag controller the jtag controller (jtagc) block provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode. all data input to and output from the jtagc block is communicated in serial format. the jtagc block is compliant with the ieee standard. the jtag controller provides the following features: ieee test access port (tap) interface 4 pins (tdi, tms, tck, tdo) selectable modes of operation include jtagc/debug or normal system operation. 5-bit instruction register that supports the following ieee 1149.1-2001 defined instructions: ? bypass ? idcode ?extest ? sample ? sample/preload 5-bit instruction register that supports the additional following public instructions: ? access_aux_tap_npc ? access_aux_tap_once 3 test data registers: ? bypass register ? boundary scan register (size parameterized to support a variety of boundary scan chain lengths) ? device identification register tap controller state machine that controls the operation of the data registers, instruction register and associated circuitry
introduction spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 28/103 doc id 16100 rev 7 1.5.31 on-chip voltage regulator (vreg) the on-chip voltage regulator module provides the following features: uses external npn (negative-positive-negative) transistor regulates external 3.3 v/5.0 v down to 1.2 v for the core logic low voltage detection on the internal 1.2 v and i/o voltage 3.3 v
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 package pinouts and signal descrip- doc id 16100 rev 7 29/103 2 package pinouts and signal descriptions 2.1 package pinouts the lqfp pinouts are shown in the following figures. for pin signal descriptions, please refer to table 7 . figure 2. 64-pin lqfp pinout ? full featured configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 nmi a[6] a[7] a[8] a[5] vdd_hv_io1 vss_hv_io1 d[9] vdd_hv_osc vss_hv_osc xtal extal reset d[8] vss_lv_cor0 vdd_lv_cor0 a[4] vpp_test d[14]] d[12] d[13 vss_lv_cor1 vdd_lv_cor1 a[3] vdd_hv_io2 vss_hv_io2 tdo tck tms tdi c[12] c[11] d[7] e[1] c[1] b[7] c[2] b[8] e[2] b[9] b[10] b[11] b[12] vdd_hv_adc0 vss_hv_adc0 e[3]/b[13] bctrl vdd_hv_reg a[15] a[14] b[6] a[13] a[9] vss_lv_cor2 vdd_lv_cor2 c[8] vss_hv_io3 vdd_hv_io3 a[12] a[11] a[10] b[2] b[1] b[0] lqfp64
package pinouts and signal descriptions spc560p34l1, spc560p34l3, SPC560P40L1, 30/103 doc id 16100 rev 7 figure 3. 64-pin lqfp pinout ? airbag configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 nmi a[6] a[7] a[8] a[5] vdd_hv_io1 vss_hv_io1 d[9] vdd_hv_osc vss_hv_osc xtal extal reset d[8] vss_lv_cor0 vdd_lv_cor0 a[4] vpp_test d[14] d[12] d[13] vss_lv_cor1 vdd_lv_cor1 a[3] vdd_hv_io2 vss_hv_io2 tdo tck tms tdi c[12] c[11] d[7] e[1] c[1] b[7] c[2] b[8] e[2] b[9] b[10] b[11] b[12] vdd_hv_adc0 vss_hv_adc0 e[3]/b[13] bctrl vdd_hv_reg a[15] a[14] b[6] a[13] a[9] vss_lv_cor2 vdd_lv_cor2 c[8] vss_hv_io3 vdd_hv_io3 a[12] a[11] a[10] b[2] b[1]] b[0] lqfp64
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 package pinouts and signal descrip- doc id 16100 rev 7 31/103 figure 4. 100-pin lqfp pinout ? full featured configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 nmi a[6] d[1] a[7] c[4] a[8] c[5] a[5] c[7] c[3] n.c. n.c. vdd_hv_io1 vss_hv_io1 d[9] vdd_hv_osc vss_hv_osc xtal extal reset d[8] d[5] d[6] vss_lv_cor0 vdd_lv_cor0 a[4] vpp_test d[14] c[14] c[13] d[12] n.c. n.c. d[13] vss_lv_cor1 vdd_lv_cor1 a[3] vdd_hv_io2 vss_hv_io2 tdo tck tms tdi a[2] c[12] c[11] d[11] d[10] a[1] a[0] d[7] e[1] c[1] b[7] c[2] b[8] e[2] n.c. n.c. b[9] b[10] b[11] b[12] vdd_hv_adc0 vss_hv_adc0 e[7]/d[15] e[3]/b[13] e[5]/b[15] e[4]/b[14] e[6]/c[0] n.c. bctrl n.c. n.c. vdd_hv_reg a[15] a[14] c[6] d[2] b[6] a[13] a[9] vss_lv_cor2 vdd_lv_cor2 c[8] d[4] d[3] vss_hv_io3 vdd_hv_io3 d[0] c[15] c[9] a[12] a[11] a[10] b[3] b[2] c[10] b[1] b[0] lqfp100
package pinouts and signal descriptions spc560p34l1, spc560p34l3, SPC560P40L1, 32/103 doc id 16100 rev 7 figure 5. 100-pin lqfp pinout ? airbag configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 nmi a[6] d[1] a[7] c[4] a[8] c[5] a[5] c[7] c[3] n.c. n.c. vdd_hv_io1 vss_hv_io1 d[9] vdd_hv_osc vss_hv_osc xtal extal reset d[8] d[5] d[6] vss_lv_cor0 vdd_lv_cor0 a[4] vpp_test d[14] c[14] c[13] d[12] n.c. n.c. d[13] vss_lv_cor1 vdd_lv_cor1 a[3] vdd_hv_io2 vss_hv_io2 tdo tck tms tdi a[2] c[12] c[11] d[11] d[10] a[1] a[0] d[7] e[1] c[1] b[7] c[2] b[8] e[2] n.c. n.c. b[9] b[10] b[11] b[12] vdd_hv_adc0 vss_hv_adc0 e[7]/d[15] e[3]/b[13] e[5]/b[15] e[4]/b[14] e[6]/c[0] n.c. bctrl n.c. n.c. vdd_hv_reg a[15] a[14] c[6] d[2] b[6] a[13] a[9] vss_lv_cor2 vdd_lv_cor2 c[8] d[4] d[3] vss_hv_io3 vdd_hv_io3 d[0] c[15] c[9] a[12] a[11] a[10] b[3] b[2] c[10] b[1] b[0] lqfp100
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 package pinouts and signal descrip- doc id 16100 rev 7 33/103 2.2 pin description the following sections provide signal descriptions and related information about the functionality and configuration of the spc560p34/spc560p40 devices. 2.2.1 power supply and reference voltage pins ta ble 5 lists the power supply and reference voltage for the spc560p34/spc560p40 devices. table 5. supply pins supply pin symbol description 64-pin 100-pin vreg control and power supply pins. pins available on 64-pin and 100-pin packages bctrl voltage regulator external npn ballast base control pin 31 47 v dd_hv_reg (3.3 v or 5.0 v) voltage regulator supply voltage 32 50 adc_0 reference and supply voltage. pins available on 64-pin and 100-pin packages v dd_hv_adc0 (1) adc_0 supply and high reference voltage 28 39 v ss_hv_adc0 adc_0 ground and low reference voltage 29 40 power supply pins (3.3 v or 5.0 v). pins available on 64-pin and 100-pin packages v dd_hv_io1 input/output supply voltage 6 13 v ss_hv_io1 input/output ground 7 14 v dd_hv_io2 input/output supply voltage and data flash memory supply voltage 40 63 v ss_hv_io2 input/output ground and flash memory hv ground 39 62 v dd_hv_io3 input/output supply voltage and code flash memory supply voltage 55 87 v ss_hv_io3 input/output ground and code flash memory hv ground 56 88 v dd_hv_osc crystal oscillator amplifier supply voltage 9 16 v ss_hv_osc crystal oscillator amplifier ground 10 17 power supply pins (1.2 v). pins available on 64-pin and 100-pin packages v dd_lv_cor0 1.2 v supply pins for core logic and pll. decoupling capacitor must be connected between these pins and the nearest v ss_lv_cor pin. 16 25 v ss_lv_cor0 1.2 v supply pins for core logic and pll. decoupling capacitor must be connected between these pins and the nearest v dd_lv_cor pin. 15 24 v dd_lv_cor1 1.2 v supply pins for core logic and data flash. decoupling capacitor must be connected between these pins and the nearest v ss_lv_cor pin. 42 65 v ss_lv_cor1 1.2 v supply pins for core logic and data flash. decoupling capacitor must be connected between these pins and the nearest v dd_lv_cor pin. 43 66
package pinouts and signal descriptions spc560p34l1, spc560p34l3, SPC560P40L1, 34/103 doc id 16100 rev 7 2.2.2 system pins ta ble 6 and table 7 contain information on pin functions for the spc560p34/spc560p40 devices. the pins listed in ta ble 6 are single-function pins. the pins shown in table 7 are multi-function pins, programmable via their respective pad configuration register (pcr) values. v dd_lv_cor2 1.2 v supply pins for core logic and code flash. decoupling capacitor must be connected between these pins and the nearest v ss_lv_cor pin. 58 92 v ss_lv_cor2 1.2 v supply pins for core logic and code flash. decoupling capacitor must be connected betwee.n these pins and the nearest v dd_lv_cor pin. 59 93 1. analog supply/ground and high/low reference lines are intern ally physically separate, but are shorted via a double-bonding connection on v dd_hv_adcx /v ss_hv_adcx pins. table 5. supply pins (continued) supply pin symbol description 64-pin 100-pin table 6. system pins symbol description direction pad speed (1) pin src = 0 src = 1 64-pin 100-pin dedicated pins nmi non-maskable interrupt input only slow ? 1 1 xtal analog output of the oscillator amplifier circuit?needs to be grounded if oscillator is used in bypass mode ???1118 extal analog input of the oscillator amplifier circuit, when the oscillator is not in bypass mode analog input for the clock generator when the oscillator is in bypass mode ???1219 tdi jtag test data input input only slow ? 35 58 tms jtag state machine control input only slow ? 36 59 tck jtag clock input only slow ? 37 60 tdo jtag test data output output only slow fast 38 61 reset pin reset bidirectional reset with schmitt trigger characteristics and noise filter bidirectional medium ? 13 20 tes t p i n vpp_test pin for testing purpose only. to be tied to ground in normal operating mode. ???4774 1. src values refer to the value assigned to the slew rate control bits of the pad configuration register.
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 package pinouts and signal descrip- doc id 16100 rev 7 35/103 2.2.3 pin multiplexing ta ble 7 defines the pin list and muxing for the spc560p34/spc560p40 devices. each row of ta ble 7 shows all the possible ways of configuring each pin, via alternate functions. the default function assigned to each pin after reset is the alt0 function. spc560p34/spc560p40 devices provide three main i/o pad types, depending on the associated functions: slow pads are the most common, providing a compromise between transition time and low electromagnetic emission. medium pads provide fast enough transition for serial communication channels with controlled current to reduce electromagnetic emission. fast pads provide maximum speed. they are used for improved nexus debugging capability. medium and fast pads can use slow configuration to reduce electromagnetic emission, at the cost of reducing ac performance. for more information, see ?pad ac specifications? in the device datasheet. table 7. pin muxing port pin pcr register alternate function (1),(2) functions peripheral (3) i/o direc- tion (4) pad speed (5) pin src = 0 src = 1 64-pin 100-pin port a (16-bit) a[0] pcr[0] alt0 alt1 alt2 alt3 ? gpio[0] etc[0] sck f[0] eirq[0] siul etimer_0 dspi_2 fcu_0 siul i/o i/o i/o o i slow medium ? 51 a[1] pcr[1] alt0 alt1 alt2 alt3 ? gpio[1] etc[1] sout f[1] eirq[1] siul etimer_0 dspi_2 fcu_0 siul i/o i/o o o i slow medium ? 52 a[2] pcr[2] alt0 alt1 alt2 alt3 ? ? ? gpio[2] etc[2] ? a[3] sin abs[0] eirq[2] siul etimer_0 ? flexpwm_0 dspi_2 mc_rgm siul i/o i/o ? o i i i slow medium ? 57 a[3] pcr[3] alt0 alt1 alt2 alt3 ? ? gpio[3] etc[3] cs0 b[3] abs[1] eirq[3] siul etimer_0 dspi_2 flexpwm_0 mc_rgm siul i/o i/o i/o o i i slow medium 41 64
package pinouts and signal descriptions spc560p34l1, spc560p34l3, SPC560P40L1, 36/103 doc id 16100 rev 7 a[4] pcr[4] alt0 alt1 alt2 alt3 ? ? gpio[4] ? cs1 etc[4] fab eirq[4] siul ? dspi_2 etimer_0 mc_rgm siul i/o ? o i/o i i slow medium 48 75 a[5] pcr[5] alt0 alt1 alt2 alt3 ? gpio[5] cs0 ? cs7 eirq[5] siul dspi_1 ? dspi_0 siul i/o i/o ? o i slow medium 5 8 a[6] pcr[6] alt0 alt1 alt2 alt3 ? gpio[6] sck ? ? eirq[6] siul dspi_1 ? ? siul i/o i/o ? ? i slow medium 2 2 a[7] pcr[7] alt0 alt1 alt2 alt3 ? gpio[7] sout ? ? eirq[7] siul dspi_1 ? ? siul i/o o ? ? i slow medium 3 4 a[8] pcr[8] alt0 alt1 alt2 alt3 ? ? gpio[8] ? ? ? sin eirq[8] siul ? ? ? dspi_1 siul i/o ? ? ? i i slow medium 4 6 a[9] pcr[9] alt0 alt1 alt2 alt3 ? gpio[9] cs1 ? b[3] fault[0] siul dspi_2 ? flexpwm_0 flexpwm_0 i/o o ? o i slow medium 60 94 a[10] pcr[10] alt0 alt1 alt2 alt3 ? gpio[10] cs0 b[0] x[2] eirq[9] siul dspi_2 flexpwm_0 flexpwm_0 siul i/o i/o o o i slow medium 52 81 table 7. pin muxing (continued) port pin pcr register alternate function (1),(2) functions peripheral (3) i/o direc- tion (4) pad speed (5) pin src = 0 src = 1 64-pin 100-pin
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 package pinouts and signal descrip- doc id 16100 rev 7 37/103 a[11] pcr[11] alt0 alt1 alt2 alt3 ? gpio[11] sck a[0] a[2] eirq[10] siul dspi_2 flexpwm_0 flexpwm_0 siul i/o i/o o o i slow medium 53 82 a[12] pcr[12] alt0 alt1 alt2 alt3 ? gpio[12] sout a[2] b[2] eirq[11] siul dspi_2 flexpwm_0 flexpwm_0 siul i/o o o o i slow medium 54 83 a[13] pcr[13] alt0 alt1 alt2 alt3 ? ? ? gpio[13] ? b[2] ? sin fault[0] eirq[12] siul ? flexpwm_0 ? dspi_2 flexpwm_0 siul i/o ? o ? i i i slow medium 61 95 a[14] pcr[14] alt0 alt1 alt2 alt3 ? gpio[14] txd ? ? eirq[13] siul safety port_0 ? ? siul i/o o ? ? i slow medium 63 99 a[15] pcr[15] alt0 alt1 alt2 alt3 ? ? gpio[15] ? ? ? rxd eirq[14] siul ? ? ? safety port_0 siul i/o ? ? ? i i slow medium 64 100 port b (16-bit) b[0] pcr[16] alt0 alt1 alt2 alt3 ? gpio[16] txd ? debug[0] eirq[15] siul flexcan_0 ? sscm siul i/o o ? ? i slow medium 49 76 b[1] pcr[17] alt0 alt1 alt2 alt3 ? ? gpio[17] ? ? debug[1] rxd eirq[16] siul ? ? sscm flexcan_0 siul i/o ? ? ? i i slow medium 50 77 table 7. pin muxing (continued) port pin pcr register alternate function (1),(2) functions peripheral (3) i/o direc- tion (4) pad speed (5) pin src = 0 src = 1 64-pin 100-pin
package pinouts and signal descriptions spc560p34l1, spc560p34l3, SPC560P40L1, 38/103 doc id 16100 rev 7 b[2] pcr[18] alt0 alt1 alt2 alt3 ? gpio[18] txd ? debug[2] eirq[17] siul lin_0 ? sscm siul i/o o ? ? i slow medium 51 79 b[3] pcr[19] alt0 alt1 alt2 alt3 ? gpio[19] ? ? debug[3] rxd siul ? ? sscm lin_0 i/o ? ? ? i slow medium ? 80 b[6] pcr[22] alt0 alt1 alt2 alt3 ? gpio[22] clkout cs2 ? eirq[18] siul control dspi_2 ? siul i/o o o ? i slow medium 62 96 b[7] pcr[23] alt0 alt1 alt2 alt3 ? ? gpio[23] ? ? ? an[0] rxd siul ? ? ? adc_0 lin_0 input only ? ? 20 29 b[8] pcr[24] alt0 alt1 alt2 alt3 ? ? gpio[24] ? ? ? an[1] etc[5] siul ? ? ? adc_0 etimer_0 input only ? ? 22 31 b[9] pcr[25] alt0 alt1 alt2 alt3 ? gpio[25] ? ? ? an[11] siul ? ? ? adc_0 input only ? ? 24 35 b[10] pcr[26] alt0 alt1 alt2 alt3 ? gpio[26] ? ? ? an[12] siul ? ? ? adc_0 input only ? ? 25 36 table 7. pin muxing (continued) port pin pcr register alternate function (1),(2) functions peripheral (3) i/o direc- tion (4) pad speed (5) pin src = 0 src = 1 64-pin 100-pin
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 package pinouts and signal descrip- doc id 16100 rev 7 39/103 b[11] pcr[27] alt0 alt1 alt2 alt3 ? gpio[27] ? ? ? an[13] siul ? ? ? adc_0 input only ? ? 26 37 b[12] pcr[28] alt0 alt1 alt2 alt3 ? gpio[28] ? ? ? an[14] siul ? ? ? adc_0 input only ? ? 27 38 b[13] pcr[29] alt0 alt1 alt2 alt3 ? ? ? gpio[29] ? ? ? an[6] emu. an[0] rxd siul ? ? ? adc_0 emu. adc_1 (6) lin_1 input only ? ? 30 42 b[14] pcr[30] alt0 alt1 alt2 alt3 ? ? ? ? gpio[30] ? ? ? an[7] emu. an[1] etc[4] eirq[19] siul ? ? ? adc_0 emu. adc_1 (6) etimer_0 siul input only ? ? ? 44 b[15] pcr[31] alt0 alt1 alt2 alt3 ? ? ? gpio[31] ? ? ? an[8] emu. an[2] eirq[20] siul ? ? ? adc_0 emu. adc_1 (6) siul input only ? ? ? 43 port c (16-bit) c[0] pcr[32] alt0 alt1 alt2 alt3 ? ? gpio[32] ? ? ? an[9] emu. an[3] siul ? ? ? adc_0 emu. adc_1 (6) input only ? ? ? 45 table 7. pin muxing (continued) port pin pcr register alternate function (1),(2) functions peripheral (3) i/o direc- tion (4) pad speed (5) pin src = 0 src = 1 64-pin 100-pin
package pinouts and signal descriptions spc560p34l1, spc560p34l3, SPC560P40L1, 40/103 doc id 16100 rev 7 c[1] pcr[33] alt0 alt1 alt2 alt3 ? gpio[33] ? ? ? an[2] siul ? ? ? adc_0 input only ? ? 19 28 c[2] pcr[34] alt0 alt1 alt2 alt3 ? gpio[34] ? ? ? an[3] siul ? ? ? adc_0 input only ? ? 21 30 c[3] pcr[35] alt0 alt1 alt2 alt3 ? gpio[35] cs1 ? txd eirq[21] siul dspi_0 ? lin_1 siul i/o o ? o i slow medium ? 10 c[4] pcr[36] alt0 alt1 alt2 alt3 ? gpio[36] cs0 x[1] debug[4] eirq[22] siul dspi_0 flexpwm_0 sscm siul i/o i/o o ? i slow medium ? 5 c[5] pcr[37] alt0 alt1 alt2 alt3 ? gpio[37] sck ? debug[5] eirq[23] siul dspi_0 ? sscm siul i/o i/o ? ? i slow medium ? 7 c[6] pcr[38] alt0 alt1 alt2 alt3 ? gpio[38] sout b[1] debug[6] eirq[24] siul dspi_0 flexpwm_0 sscm siul i/o o o ? i slow medium ? 98 c[7] pcr[39] alt0 alt1 alt2 alt3 ? gpio[39] ? a[1] debug[7] sin siul ? flexpwm_0 sscm dspi_0 i/o ? o ? i slow medium ? 9 c[8] pcr[40] alt0 alt1 alt2 alt3 gpio[40] cs1 ? cs6 siul dspi_1 ? dspi_0 i/o o ? o slow medium 57 91 table 7. pin muxing (continued) port pin pcr register alternate function (1),(2) functions peripheral (3) i/o direc- tion (4) pad speed (5) pin src = 0 src = 1 64-pin 100-pin
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 package pinouts and signal descrip- doc id 16100 rev 7 41/103 c[9] pcr[41] alt0 alt1 alt2 alt3 gpio[41] cs3 ? x[3] siul dspi_2 ? flexpwm_0 i/o o ? o slow medium ? 84 c[10] pcr[42] alt0 alt1 alt2 alt3 ? gpio[42] cs2 ? a[3] fault[1] siul dspi_2 ? flexpwm_0 flexpwm_0 i/o o ? o i slow medium ? 78 c[11] pcr[43] alt0 alt1 alt2 alt3 gpio[43] etc[4] cs2 ? siul etimer_0 dspi_2 ? i/o i/o o ? slow medium 33 55 c[12] pcr[44] alt0 alt1 alt2 alt3 gpio[44] etc[5] cs3 ? siul etimer_0 dspi_2 ? i/o i/o o ? slow medium 34 56 c[13] pcr[45] alt0 alt1 alt2 alt3 ? ? gpio[45] ? ? ? ext_in ext_sync siul ? ? ? ctu_0 flexpwm_0 i/o ? ? ? i i slow medium ? 71 c[14] pcr[46] alt0 alt1 alt2 alt3 gpio[46] ? ext_tgr ? siul ? ctu_0 ? i/o ? o ? slow medium ? 72 c[15] pcr[47] alt0 alt1 alt2 alt3 ? ? gpio[47] ? ? a[1] ext_in ext_sync siul ? ? flexpwm_0 ctu_0 flexpwm_0 i/o ? ? o i i slow medium ? 85 port d (16-bit) d[0] pcr[48] alt0 alt1 alt2 alt3 gpio[48] ? ? b[1] siul ? ? flexpwm_0 i/o ? ? o slow medium ? 86 table 7. pin muxing (continued) port pin pcr register alternate function (1),(2) functions peripheral (3) i/o direc- tion (4) pad speed (5) pin src = 0 src = 1 64-pin 100-pin
package pinouts and signal descriptions spc560p34l1, spc560p34l3, SPC560P40L1, 42/103 doc id 16100 rev 7 d[1] pcr[49] alt0 alt1 alt2 alt3 gpio[49] ? ? ext_trg siul ? ? ctu_0 i/o ? ? o slow medium ? 3 d[2] pcr[50] alt0 alt1 alt2 alt3 gpio[50] ? ? x[3] siul ? ? flexpwm_0 i/o ? ? o slow medium ? 97 d[3] pcr[51] alt0 alt1 alt2 alt3 gpio[51] ? ? a[3] siul ? ? flexpwm_0 i/o ? ? o slow medium ? 89 d[4] pcr[52] alt0 alt1 alt2 alt3 gpio[52] ? ? b[3] siul ? ? flexpwm_0 i/o ? ? o slow medium ? 90 d[5] pcr[53] alt0 alt1 alt2 alt3 gpio[53] cs3 f[0] ? siul dspi_0 fcu_0 ? i/o o o ? slow medium ? 22 d[6] pcr[54] alt0 alt1 alt2 alt3 ? gpio[54] cs2 ? ? fault[1] siul dspi_0 ? ? flexpwm_0 i/o o ? ? i slow medium ? 23 d[7] pcr[55] alt0 alt1 alt2 alt3 gpio[55] cs3 f[1] cs4 siul dspi_1 fcu_0 dspi_0 i/o o o o slow medium 17 26 d[8] pcr[56] alt0 alt1 alt2 alt3 gpio[56] cs2 ? cs5 siul dspi_1 ? dspi_0 i/o o ? o slow medium 14 21 d[9] pcr[57] alt0 alt1 alt2 alt3 gpio[57] x[0] txd ? siul flexpwm_0 lin_1 ? i/o o o ? slow medium 8 15 d[10] pcr[58] alt0 alt1 alt2 alt3 gpio[58] a[0] ? ? siul flexpwm_0 ? ? i/o o ? ? slow medium ? 53 table 7. pin muxing (continued) port pin pcr register alternate function (1),(2) functions peripheral (3) i/o direc- tion (4) pad speed (5) pin src = 0 src = 1 64-pin 100-pin
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 package pinouts and signal descrip- doc id 16100 rev 7 43/103 d[11] pcr[59] alt0 alt1 alt2 alt3 gpio[59] b[0] ? ? siul flexpwm_0 ? ? i/o o ? ? slow medium ? 54 d[12] pcr[60] alt0 alt1 alt2 alt3 ? gpio[60] x[1] ? ? rxd siul flexpwm_0 ? ? lin_1 i/o o ? ? i slow medium 45 70 d[13] pcr[61] alt0 alt1 alt2 alt3 gpio[61] a[1] ? ? siul flexpwm_0 ? ? i/o o ? ? slow medium 44 67 d[14] pcr[62] alt0 alt1 alt2 alt3 gpio[62] b[1] ? ? siul flexpwm_0 ? ? i/o o ? ? slow medium 46 73 d[15] pcr[63] alt0 alt1 alt2 alt3 ? ? gpio[63] ? ? ? an[10] emu. an[4] siul ? ? ? adc_0 emu. adc_1 (6) input only ? ? ? 41 port e (16-bit) e[1] pcr[65] alt0 alt1 alt2 alt3 ? gpio[65] ? ? ? an[4] siul ? ? ? adc_0 input only ? ? 18 27 e[2] pcr[66] alt0 alt1 alt2 alt3 ? gpio[66] ? ? ? an[5] siul ? ? ? adc_0 input only ? ? 23 32 e[3] pcr[67] alt0 alt1 alt2 alt3 ? gpio[67] ? ? ? an[6] siul ? ? ? adc_0 input only ? ? 30 42 table 7. pin muxing (continued) port pin pcr register alternate function (1),(2) functions peripheral (3) i/o direc- tion (4) pad speed (5) pin src = 0 src = 1 64-pin 100-pin
package pinouts and signal descriptions spc560p34l1, spc560p34l3, SPC560P40L1, 44/103 doc id 16100 rev 7 e[4] pcr[68] alt0 alt1 alt2 alt3 ? gpio[68] ? ? ? an[7] siul ? ? ? adc_0 input only ? ? ? 44 e[5] pcr[69] alt0 alt1 alt2 alt3 ? gpio[69] ? ? ? an[8] siul ? ? ? adc_0 input only ? ? ? 43 e[6] pcr[70] alt0 alt1 alt2 alt3 ? gpio[70] ? ? ? an[9] siul ? ? ? adc_0 input only ? ? ? 45 e[7] pcr[71] alt0 alt1 alt2 alt3 ? gpio[71] ? ? ? an[10] siul ? ? ? adc_0 input only ? ? ? 41 1. alt0 is the primary (default) function for each port after reset. 2. alternate functions are chosen by setting the values of the pcr.pa bitfields inside the siu module. pcr.pa = 00 alt0; pcr.pa = 01 alt1; pcr.pa = 10 alt2; pcr.pa = 11 alt3. this is intended to select the output functions; to use one of the input functions, the pcr.ibe bit must be written to ?1?, regardless of the values selected in the pcr.pa bitfields. for this reason, the value correspondi ng to an input only function is reported as ???. 3. module included on the mcu. 4. multiple inputs are routed to all respective modules internally . the input of some modules must be configured by setting the values of the psmio.padselx bitfields inside the siul module. 5. programmable via the src (slew rate control) bits in the respective pad configuration register. 6. adc0.an emulates adc1.an. this feature is used to provide software compatibility between spc560p34/spc560p40 and spc560p50. refer to adc chapter of reference manual for more details. table 7. pin muxing (continued) port pin pcr register alternate function (1),(2) functions peripheral (3) i/o direc- tion (4) pad speed (5) pin src = 0 src = 1 64-pin 100-pin
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 electrical characteristics doc id 16100 rev 7 45/103 3 electrical characteristics 3.1 introduction this section contains device electrical characteristics as well as temperature and power considerations. this microcontroller contains input protection against damage due to high static voltages. however, it is advisable to take precautions to avoid application of any voltage higher than the specified maximum rated voltages. to enhance reliability, unused inputs can be driven to an appropriate logic voltage level (v dd or v ss ). this can be done by the internal pull-up or pull-down resistors, which are provided by the device for most general purpose pins. the following tables provide the device characteristics and its demands on the system. in the tables where the device logic provides signals with their respective timing characteristics, the symbol ?cc? for controller characteristics is included in the symbol column. in the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol ?sr? for system requirement is included in the symbol column. caution: all of the following parameter values can vary depending on the application and must be confirmed during silicon characterization or silicon reliability trial. 3.2 parameter classification the electrical parameters are guaranteed by various methods. to give the customer a better understanding, the classifications listed in table 8 are used and the parameters are tagged accordingly in the tables where appropriate. note: the classification is shown in the column labeled ?c? in the parameter tables where appropriate. table 8. parameter classifications classification tag tag description p those parameters are guaranteed during production testing on each individual device. c those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. t those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. all values shown in the typical column are within this category. d those parameters are derived mainly from simulations.
electrical characteristics spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 46/103 doc id 16100 rev 7 3.3 absolute maximum ratings table 9. absolute maximum ratings (1) symbol parameter conditions value unit min max (2) v ss s r device ground ? 0 0 v v dd_hv_iox (3) s r 3.3 v/5.0 v input/output supply voltage (supply). code flash memory supply with v dd_hv_io3 and data flash memory with v dd_hv_io2 ? ?0.3 6.0 v v ss_hv_iox s r 3.3 v/5.0 v input/output supply voltage (ground). code flash memory ground with v ss_hv_io3 and data flash memory with v ss_hv_io2 ? ?0.1 0.1 v v dd_hv_osc s r 3.3 v/5.0 v crystal oscillator amplifier supply voltage (supply) ? ?0.3 6.0 v relative to v dd_hv_iox ?0.3 v dd_hv_iox +0.3 v ss_hv_osc s r 3.3 v/5.0 v crystal oscillator amplifier supply voltage (ground) ? ?0.1 0.1 v v dd_hv_adc0 s r 3.3 v/5.0 v adc_0 supply and high- reference voltage v dd_hv_reg < 2.7 v ?0.3 v dd_hv_reg +0.3 v v dd_hv_reg > 2.7 v ?0.3 6.0 v ss_hv_adc0 s r 3.3 v/5.0 v adc_0 ground and low- reference voltage ? ?0.1 0.1 v v dd_hv_reg s r 3.3 v/5.0 v voltage-regulator supply voltage ? ?0.3 6.0 v relative to v dd_hv_iox ?0.3 v dd_hv_iox +0.3 tv dd s r slope characteristics on all v dd during power up (4) with respect to ground (v ss ) ?3.0 (5) 500 x 10 3 (0.5 [v/s]) v/s v dd_lv_corx c c 1.2 v supply pins for core logic (supply) ? ?0.1 1.5 v v ss_lv_corx s r 1.2 v supply pins for core logic (ground) ? ?0.1 0.1 v v in s r voltage on any pin with respect to ground (v ss_hv_iox ) ? ?0.3 6.0 v relative to v dd_hv_iox ?0.3 v dd_hv_iox +0.3 (6) i injpad s r input current on any pin during overload condition ? ?10 10 ma
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 electrical characteristics doc id 16100 rev 7 47/103 figure 6 shows the constraints of the different power supplies. figure 6. power supplies constraints (?0.3 v v dd_hv_iox 6.0 v) the spc560p34/spc560p40 supply architecture allows the adc supply to be managed independently from the standard v dd_hv supply. figure 7 shows the constraints of the adc power supply. i injsum s r absolute sum of all input currents during overload condition ? ?50 50 ma t stg s r storage temperature ? ?55 150 c t j s r junction temperature under bias ? ? 40 150 c 1. functional operating conditions are given in the dc electrical characteristics. absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. stress beyond the listed maxima may affect device reliability or cause permanent damage to the device. 2. absolute maximum voltages are currently maximum burn-in voltages. 3. the difference between each couple of voltage supplies must be less than 300 mv, ? v dd_hv_ioy ?v dd_hv_iox ? < 300 mv. 4. guaranteed by device validation. 5. minimum value of tv dd must be guaranteed until v dd_hv_reg reaches 2.6 v (maximum value of v porh ) 6. only when v dd_hv_iox < 5.2 v table 9. absolute maximum ratings (1) (continued) symbol parameter conditions value unit min max (2) vdd_hv_xxx vdd_hv_iox ?0.3 v 6.0 v ?0.3 v 6.0 v
electrical characteristics spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 48/103 doc id 16100 rev 7 figure 7. independent adc supply (?0.3 v v dd_hv_reg 6.0 v) 3.4 recommended operating conditions vdd_hv_adcx 6.0 v vdd_hv_reg ?0.3 v 2.7 v ?0.3 v 6.0 v table 10. recommended operating conditions (5.0 v) symbol parameter conditions value unit min max (1) v ss sr device ground ? 0 0 v v dd_hv_iox (2) sr 5.0 v input/output supply voltage ?4.55.5v v ss_hv_iox sr input/output ground voltage ?0 0v v dd_hv_osc sr 5.0 v crystal oscillator amplifier supply voltage ?4.55.5 v relative to v dd_hv_iox v dd_hv_iox ?0.1 v dd_hv_iox +0.1 v ss_hv_osc sr 5.0 v crystal oscillator amplifier reference voltage ?0 0v v dd_hv_reg sr 5.0 v voltage regulator supply voltage ?4.55.5 v relative to v dd_hv_iox v dd_hv_iox ?0.1 v dd_hv_iox +0.1
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 electrical characteristics doc id 16100 rev 7 49/103 v dd_hv_adc0 sr 5.0 v adc_0 supply and high reference voltage ?4.55.5 v relative to v dd_hv_reg v dd_hv_reg ?0.1 ? v ss_hv_adc0 sr adc_0 ground and low reference voltage ?0 0v v dd_lv_regcor (3) ,(4) cc internal supply voltage ? ? ? v v ss_lv_regcor (3) sr internal reference voltage ?0 0v v dd_lv_corx (3),(4) cc internal supply voltage ? ? ? v v ss_lv_corx (3) sr internal reference voltage ?0 0v t a sr ambient temperature under bias f cpu =60mhz ? 40 125 c f cpu =64mhz ? 40 105 c 1. full functionality cannot be guaranteed when voltage drops below 4.5 v. in particular, adc electrical characteristics and i/os dc electrical specif ication may not be guaranteed. 2. the difference between each couple of voltage supplies must be less than 100 mv, ? v dd_hv_ioy ? v dd_hv_iox ? < 100 mv. 3. to be connected to emitter of external npn. low voltage supplies are not under user cont rol?they are produced by an on- chip voltage regulator?but for the device to function properly the low voltage grounds (v ss_lv_xxx ) must be shorted to high voltage grounds (v ss_hv_xxx ) and the low voltage supply pins (v dd_lv_xxx ) must be connected to the external ballast emitter. 4. the low voltage supplies (v dd_lv_xxx ) are not all independent. ? v dd_lv_cor1 and v dd_lv_cor2 are shorted internally via double bonding connec tions with lines that provide the low voltage supply to the data flash memory module. similarly, v ss_lv_cor1 and v ss_lv_cor2 are internally shorted. ? v dd_lv_regcor and v dd_lv_recorx are physically shorted internally, as are v ss_lv_regcor and v ss_lv_corx . table 10. recommended operating conditions (5.0 v) (continued) symbol parameter conditions value unit min max (1) table 11. recommended operating conditions (3.3 v) symbol parameter conditions value unit min max (1) v ss sr device ground ? 0 0 v v dd_hv_iox (2) sr 3.3 v input/output supply voltage ?3.03.6v v ss_hv_iox sr input/output ground voltage ?00v v dd_hv_osc sr 3.3 v crystal oscillator amplifier supply voltage ?3.03.6 v relative to v dd_hv_iox v dd_hv_iox ?0.1 v dd_hv_iox +0.1 v ss_hv_osc sr 3.3 v crystal oscillator amplifier reference voltage ?00v
electrical characteristics spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 50/103 doc id 16100 rev 7 figure 8 shows the constraints of the different power supplies. v dd_hv_reg sr 3.3 v voltage regulator supply voltage ?3.03.6 v relative to v dd_hv_iox v dd_hv_iox ?0.1 v dd_hv_iox +0.1 v dd_hv_adc0 sr 3.3 v adc_0 supply and high reference voltage ?3.05.5 v relative to v dd_hv_reg v dd_hv_reg ? 0.1 5.5 v ss_hv_adc0 sr adc_0 ground and low reference voltage ?00v v dd_lv_regcor (3) ,(4) cc internal supply voltage ? ? ? v v ss_lv_regcor (3) sr internal reference voltage ?00v v dd_lv_corx (3),(4) cc internal supply voltage ? ? ? v v ss_lv_corx (3) sr internal reference voltage ?00v t a sr ambient temperature under bias f cpu =60mhz ? 40 125 c f cpu =64mhz ? 40 105 c 1. full functionality cannot be guaranteed when voltage drops below 3.0 v. in particular, adc electrical characteristics and i/os dc electrical specif ication may not be guaranteed. 2. the difference between each couple of voltage supplies must be less than 100 mv, ? v dd_hv_ioy ? v dd_hv_iox ? < 100 mv. 3. to be connected to emitter of external npn. low voltage supplies are not under user cont rol?they are produced by an on- chip voltage regulator?but for the device to function properly the low voltage grounds (v ss_lv_xxx ) must be shorted to high voltage grounds (v ss_hv_xxx ) and the low voltage supply pins (v dd_lv_xxx ) must be connected to the external ballast emitter. 4. the low voltage supplies (v dd_lv_xxx ) are not all independent. ? v dd_lv_cor1 and v dd_lv_cor2 are shorted internally via double bonding connec tions with lines that provide the low voltage supply to the data flash memory module. similarly, v ss_lv_cor1 and v ss_lv_cor2 are internally shorted. ? v dd_lv_regcor and v dd_lv_recorx are physically shorted internally, as are v ss_lv_regcor and v ss_lv_corx . table 11. recommended operating conditions (3.3 v) (continued) symbol parameter conditions value unit min max (1)
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 electrical characteristics doc id 16100 rev 7 51/103 figure 8. power supplies constraints (3.0 v v dd_hv_iox 5.5 v) the spc560p34/spc560p40 supply architecture allows the adc supply to be managed independently from the standard v dd_hv supply. figure 9 shows the constraints of the adc power supply. figure 9. independent adc supply (3.0 v v dd_hv_reg 5.5 v) vdd_hv_xxx vdd_hv_iox 3.0 v 5.5 v 3.0 v 5.5 v 3.3 v 3.3 v note : io ac and dc characteristics are guaranteed only in the range of 3.0?3.6 v when pad3v5v is low, and in the range of 4.5?5.5 v when pad3v5v is high. 5.5 v 3.0 v vdd_hv_reg 3.0 v 5.5 v vdd_hv_adcx
electrical characteristics spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 52/103 doc id 16100 rev 7 3.5 thermal characteristics 3.5.1 package thermal characteristics 3.5.2 general notes for specifications at maximum junction temperature an estimation of the chip junction temperature, t j , can be obtained from equation 1 : equation 1: t j = t a + (r ja * p d ) where: t a = ambient temperature for the package (c) r ja = junction-to-ambient thermal resistance (c/w) p d = power dissipation in the package (w) the junction-to-ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. unfortunately, there are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes. for packages such as the pbga, these values can be different by a factor of two. which value is closer to the application depends on the power dissipated by other components on the board. the value obtained on a single layer board is appropriate for the tightly packed printed circuit board. the value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. when a heat sink is used, the thermal resistance is expressed in equation 2 as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: table 12. lqfp thermal characteristics symbol parameter conditions typical value unit 100-pin 64-pin r ja thermal resistance junction-to-ambient, natural convection (1) single layer board?1s 63 57 c/w four layer board?2s2p 51 41 c/w r jb thermal resistance junction-to-board (2) four layer board?2s2p 33 22 c/w r jctop thermal resistance junction-to-case (top) (3) single layer board?1s 15 13 c/w jb junction-to-board, natural convection (4) operating conditions 33 22 c/w jc junction-to-case, natural convection (5) operating conditions 1 1 c/w 1. junction-to-ambient thermal resistance determined per jede c jesd51-7. thermal test board meets jedec specification for this package. 2. junction-to-board thermal resistance det ermined per jedec jesd51-8. thermal test board meets jedec specification for the specified package. when greek lett ers are not available, the symbol s are typed as rthjb or theta-jb. 3. junction-to-case at the top of the package determined using mil-std 883 method 1012.1. the cold plate temperature is used for the case temperature. reported value includes the thermal resistance of the interface layer. 4. thermal characterization parameter indicating the temper ature difference between the boar d and the junction temperature per jedec jesd51-2. when greek letters ar e not available, the thermal characteri zation parameter is written as psi-jb. 5. thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the therma l characterization par ameter is written as psi-jc.
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 electrical characteristics doc id 16100 rev 7 53/103 equation 2: r ja = r jc + r ca where: r ja = junction-to-ambient thermal resistance (c/w) r jc = junction-to-case thermal resistance (c/w) r ca = case-to-ambient thermal resistance (c/w) r jc is device related and cannot be influenced by the user. the user controls the thermal environment to change the case-to-ambient thermal resistance, r ca . for instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. to determine the junction temperature of the device in the application when heat sinks are not used, the thermal characterization parameter ( jt ) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using equation 3 : equation 3: t j = t t + ( jt x p d ) where: t t = thermocouple temperature on top of the package (c) jt = thermal characterization parameter (c/w) p d = power dissipation in the package (w) the thermal characterization parameter is measured per jesd51-2 specification using a 40 gauge type t thermocouple epoxied to the top center of the package case. the thermocouple should be positioned so that the thermocouple junction rests on the package. a small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. the thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. references: semiconductor equipment and materials international 3081 zanker road san jose, ca 95134u.s.a. (408) 943-6900 mil-spec and eia/jesd (jedec) specifications are available from global engineering documents at (800) 854-7179 or (303) 397-7956. jedec specifications are available on the web at http://www.jedec.org. c.e. triplett and b. joiner, an experimental characterization of a 272 pbga within an automotive engine controller module , proceedings of semitherm, san diego, 1998, pp. 47?54. g. kromann, s. shidore, and s. addison, thermal modeling of a pbga for air-cooled applications , electronic packaging and production, pp. 53?58, march 1998. b. joiner and v. adams, measurement and simulation of junction to board thermal resistance and its application in thermal modeling , proceedings of semitherm, san diego, 1999, pp. 212?220.
electrical characteristics spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 54/103 doc id 16100 rev 7 3.6 electromagnetic interference (emi) characteristics 3.7 electrostatic discharge (esd) characteristics 3.8 power management electrical characteristics 3.8.1 voltage regulator electrical characteristics the internal voltage regulator requires an external npn ballast, approved ballast list availbale in ta ble 15 , to be connected as shown in figure 10 . capacitances should be placed on the board as near as possible to the associated pins. care should also be taken to limit the serial inductance of the v dd_hv_reg , bctrl and v dd_lv_corx pins to less than l reg . (refer to tab le 16 ). table 13. emi testing specifications symbol parameter conditions clocks frequency level (typ) unit v eme radiated emissions v dd = 5.0 v; t a =25c other device configuration, test conditions and em testing per standard iec61967-2 f osc =8mhz f cpu =64mhz no pll frequency modulation 150 khz?150 mhz 11 db v 150?1000 mhz 13 iec level m ? f osc =8mhz f cpu =64mhz 4% pll frequency modulation 150 khz?150 mhz 8 db v 150?1000 mhz 12 iec level n ? v dd = 3.3 v; t a =25c other device configuration, test conditions and em testing per standard iec61967-2 f osc =8mhz f cpu =64mhz no pll frequency modulation 150 khz?150 mhz 9 db v 150?1000 mhz 12 iec level m ? f osc =8mhz f cpu =64mhz 4% pll frequency modulation 150 khz?150 mhz 7 db v 150?1000 mhz 12 iec level n ? table 14. esd ratings (1),(2) symbol parameter conditions value unit v esd(hbm) s r electrostatic discharge (human body model) ? 2000 v v esd(cdm) s r electrostatic discharge (charged device model) ? 750 (corners) v 500 (other) 1. all esd testing is in conformity with cdf-aec-q100 stress test qualification for automotive grade integrated circuits. 2. a device will be defined as a failure if after exposure to esd pulses the device no longer m eets the device specification requirements. complete dc parametric and functional test ing shall be performed per applic able device specification at room temperature followed by hot temperature, unless specified other wise in the device specification.
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 electrical characteristics doc id 16100 rev 7 55/103 note: the voltage regulator output cannot be used to drive external circuits. output pins are to be used only for decoupling capacitance. v dd_lv_cor must be generated using internal regulator and external npn transistor. it is not possible to provide v dd_lv_cor through external regulator. for the spc560p34/spc560p40 microcontroller, capacitor(s), with total values not below c dec1 , should be placed between v dd_lv_corx /v ss_lv_corx close to external ballast transistor emitter. 4 capacitors, with total values not below c dec2 , should be placed close to microcontroller pins between each v dd_lv_corx /v ss_lv_corx supply pairs and the v dd_lv_regcor /v ss_lv_regcor pair . additionally, capacitor(s) with total values not below c dec3 , should be placed between the v dd_hv_reg /v ss_hv_reg pins close to ballast collector. capacitors values have to take into account capacitor accuracy, aging and variation versus temperature. all reported information are valid for voltage and temperature ranges described in recommended operating condition, tab le 10 and table 11 . figure 10. voltage regulator configuration bctrl vdd_lv_cor c dec3 c dec2 c dec1 vdd_hv_reg bjt (1) spc560p34/spc560p 1. refer to table 15 . table 15. approved npn ballast components part manufacturer approved derivatives (1) bcp68 on semi bcp68 nxp bcp68-25 infineon bcp68-25 bcx68 infineon bcx68-10; bcx68-16; bcx-25 bc868 nxp bc868
electrical characteristics spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 56/103 doc id 16100 rev 7 bc817 infineon bc817-16; bc817-25; bc817su nxp bc817-16; bc817-25 bcp56 st bcp56-16 infineon bcp56-10; bcp56-16 on semi bcp56-10 nxp bcp56-10; bcp56-16 1. for automotive applications please check with the appropr iate transistor vendor for aut omotive grade certification table 15. approved npn ballast components part manufacturer approved derivatives (1) table 16. voltage regulator electrical characteristics symbol c parameter conditions value unit min typ max v dd_lv_regcor c c p output voltage under maximum load run supply current configuration post-trimming 1.15 ? 1.32 v c dec1 s r ? external decoupling/stability ceramic capacitor bjt from table 15 . three capacitors (i.e. x7r or x8r capacitors) with nominal value of 10 f 19.5 30 ? f bjt bc817, one capacitance of 22 f 14.3 22 ? f r reg s r ? resulting esr of either one or all three c dec1 absolute maximum value between 100 khz and 10 mhz ??45m c dec2 s r ? external decoupling/stability ceramic capacitor four capacitances (i.e. x7r or x8r capacitors) with nominal value of 440 nf 120 0 176 0 ?nf c dec3 s r ? external decoupling/stability ceramic capacitor on vdd_hv_reg three capacitors (i.e. x7r or x8r capacitors) with nominal value of 10 f; c dec3 has to be equal or greater than c dec1 19.5 30 ? f l reg s r ? resulting esl of v dd_hv_reg , bctrl and v dd_lv_corx pins ???5nh
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 electrical characteristics doc id 16100 rev 7 57/103 3.8.2 voltage monitor electrical characteristics the device implements a power on reset module to ensure correct power-up initialization, as well as three low voltage detectors to monitor the v dd and the v dd_lv voltage while device is supplied: por monitors v dd during the power-up phase to ensure device is maintained in a safe reset state lvdhv3 monitors v dd to ensure device reset below minimum functional supply lvdhv5 monitors v dd when application uses device in the 5.0 v 10% range lvdlvcor monitors low voltage digital power domain 3.9 power up/down sequencing to prevent an overstress event or a malfunction within and outside the device, the spc560p34/spc560p40 implements the following sequence to ensure each module is started only when all conditions for switching it on are available: a power_on module working on voltage regulator supply controls the correct start- up of the regulator. this is a key module ensuring safe configuration for all voltage regulator functionality when supply is below 1.5 v. associated power_on (or por) signal is active low. several low voltage detectors, working on voltage regulator supply monitor the voltage of the critical modules (voltage regulator, i/os, flash memory and low voltage domain). lvds are gated low when power_on is active. a power_ok signal is generated when all critical supplies monitored by the lvd are available. this signal is active high and released to all modules including i/os, flash table 17. low voltage monitor electrical characteristics symbol c parameter conditions (1) value unit min max v porh t power-on reset threshold ? 1.5 2.7 v v porup p supply for functional por module t a = 25 c 1.0 ? v v reglvdmok_h p regulator low voltage detector high threshold ? ? 2.95 v v reglvdmok_l p regulator low voltage detector low threshold ? 2.6 ? v v fllvdmok_h p flash low voltage detector high threshold ? ? 2.95 v v fllvdmok_l p flash low voltage detector low threshold ? 2.6 ? v v iolvdmok_h p i/o low voltage detector high threshold ? ? 2.95 v v iolvdmok_l p i/o low voltage detector low threshold ? 2.6 ? v v iolvdm5ok_h p i/o 5 v low voltage detector high threshold ? ? 4.4 v v iolvdm5ok_l p i/o 5 v low voltage detector low threshold ? 3.8 ? v v mlvddok_h p digital supply low voltage detector high ? ? 1.145 v v mlvddok_l p digital supply low voltage detector low ? 1.08 ? v 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 c to t a max , unless otherwise specified
electrical characteristics spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 58/103 doc id 16100 rev 7 memory and 16 mhz rc oscillator needed during power-up phase and reset phase. when power_ok is low the associated modules are set into a safe state. figure 11. power-up typical sequence figure 12. power-down typical sequence vdd_hv_reg 0v 3.3v 0v 3.3v vdd_lv_regcor 0v 1.2v 0v 3.3v power_on lvdm (hv) 0v lvdd (lv) 3.3v 0v power_ok 3.3v rc16mhz oscillator 0v 1.2v p0 p1 0v 1.2v internal reset generation module fsm ~1us v por_up v porh v lvdhv3h v mlvdok_h vdd_hv_reg 0v 3.3v 0v 3.3v vdd_lv_regcor 0v 1.2v 3.3v power_on lvdm (hv) 0v lvdd (lv) 3.3v 0v power_ok 3.3v rc16mhz oscillator 0v 1.2v p0 idle 0v 1.2v internal reset generation module fsm v lvdhv3l v porh 0v
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 electrical characteristics doc id 16100 rev 7 59/103 figure 13. brown-out typical sequence 3.10 dc electrical characteristics 3.10.1 nvusro register portions of the device configuration, such as high voltage supply and watchdog enable/disable after reset are controlled via bit values in the non-volatile user options (nvusro) register. for a detailed description of the nvusro register, please refer to the device reference manual. nvusro[pad3v5v] field description the dc electrical characteristics are dependent on the pad3v5v bit value. tab le 18 shows how nvusro[pad3v5v] controls the device configuration. vdd_hv_reg 0v 3.3v 0v 3.3v vdd_lv_regcor 0v 1.2v 3.3v power_on lvdm (hv) 0v lvdd (lv) 3.3v 0v power_ok 3.3v rc16mhz oscillator 0v 1.2v p0 idle 0v 1.2v internal reset generation module fsm v lvdhv3l 0v v lvdhv3h p1 ~1us table 18. pad3v5v field description value (1) 1. default manufacturing value before flash initialization is ?1? (3.3 v). description 0 high voltage supply is 5.0 v 1 high voltage supply is 3.3 v
electrical characteristics spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 60/103 doc id 16100 rev 7 3.10.2 dc electrical characteristics (5 v) ta ble 19 gives the dc electrical characteristics at 5 v (4.5 v < v dd_hv_iox < 5.5 v, nvusro[pad3v5v] = 0). table 19. dc electrical characteristics (5.0 v, nvusro[pad3v5v] = 0) symbol c parameter conditions value unit min max v il d low level input voltage ? ? 0.4 (1) ?v p??0.35v dd_hv_iox v v ih p high level input voltage ?0.65v dd_hv_iox ?v d?? v dd_hv_iox +0.4 (1) v v hys t schmitt trigger hysteresis ? 0.1 v dd_hv_iox ?v v ol_s p slow, low level output voltage i ol =3ma ? 0.1v dd_hv_iox v v oh_s p slow, high level output voltage i oh = ? 3ma 0.8v dd_hv_iox ?v v ol_m p medium, low level output voltage i ol =3ma ? 0.1v dd_hv_iox v v oh_m p medium, high level output voltage i oh = ? 3ma 0.8v dd_hv_iox ?v v ol_f p fast, low level output voltage i ol =14ma ? 0.1v dd_hv_iox v v oh_f p fast, high level output voltage i oh = ? 14 ma 0.8 v dd_hv_iox ?v i pu p equivalent pull-up current v in =v il ? 130 ? a v in =v ih ? ? 10 i pd p equivalent pull-down current v in =v il 10 ? a v in =v ih ? 130 i il p input leakage current (all bidirectional ports) t a = ? 40 to 125 c ? 11a i il p input leakage current (all adc input-only ports) t a = ? 40 to 125 c ? 0.5 0.5 a c in d input capacitance ? ? 10 pf 1. ?sr? parameter values must not exceed the absolute maximum ratings shown in table 9 .
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 electrical characteristics doc id 16100 rev 7 61/103 table 20. supply current (5.0 v, nvusro[pad3v5v] = 0) symbol c parameter conditions value (1) unit typ max i dd_lv_corx t supply current run?maximum mode (2) v dd_lv_corx externally forced at 1.3 v 40 mhz 44 55 ma p 64 mhz 52 65 t run?typical mode (3) 40 mhz 38 46 64 mhz 45 54 p halt mode (4) ?1.510 stop mode (5) ?110 i dd_flash t flash during read v dd_hv_fl at 5.0 v ? 8 10 flash during erase operation on 1 flash module v dd_hv_fl at 5.0 v ? 15 19 i dd_adc tadc v dd_hv_adc0 at 5.0 v f adc =16mhz adc_0 3 4 i dd_osc t oscillator v dd_hv_osc at 5.0 v 8 mhz 2.6 3.2 i dd_hv_reg d internal regulator module current consumption v dd_hv_reg at 5.5 v ? 10 1. all values to be confirmed afte r characterization/data collection. 2. maximum mode: flexpwm, adc, ctu, dspi, linflex, flexcan, 15 output pins, pll_0 enabled, 125 c ambient. i/o supply current excluded. 3. typical mode configurations: dspi, linflex, flexcan, 15 output pins, pll_0, 105 c ambient. i/o supply current excluded. 4. halt mode configurations: code fetched from sram, code flash memory and data flash memory in low power mode, osc/pll_0 are off, core clock frozen, all peripherals disabled. 5. stop ?p? mode device under test (dut) configuration: code fetched from sram, code flash memory and data flash memory off, osc/pll_0 are off, core clock frozen, all peripherals disabled.
electrical characteristics spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 62/103 doc id 16100 rev 7 3.10.3 dc electrical characteristics (3.3 v) ta ble 21 gives the dc electrical characteristics at 3.3 v (3.0 v < v dd_hv_iox < 3.6 v, nvusro[pad3v5v] = 1); see figure 14 . table 21. dc electrical characteristics (3.3 v, nvusro[pad3v5v] = 1) (1) symbol c parameter conditions value unit min max v il d low level input voltage ? ? 0.4 (2) ?v p??0.35v dd_hv_iox v v ih p high level input voltage ?0.65v dd_hv_iox ?v d??v dd_hv_iox +0.4 (2) v v hys t schmitt trigger hysteresis ? 0.1 v dd_hv_iox ?v v ol_s p slow, low level output voltage i ol = 1.5 ma ? 0.5 v v oh_s p slow, high level output voltage i oh = ? 1.5 ma v dd_hv_iox ? 0.8 ? v v ol_m p medium, low level output voltage i ol =2ma ? 0.5 v v oh_m p medium, high level output voltage i oh = ? 2ma v dd_hv_iox ? 0.8 ? v v ol_f p fast, low level output voltage i ol =11ma ? 0.5 v v oh_f p fast, high level output voltage i oh = ? 11 ma v dd_hv_iox ? 0.8 ? v i pu p equivalent pull-up current v in =v il ? 130 ? a v in =v ih ? ? 10 i pd p equivalent pull-down current v in =v il 10 ? a v in =v ih ?130 i il p input leakage current (all bidirectional ports) t a = ? 40 to 125 c ? 1 a i il p input leakage current (all adc input-only ports) t a = ? 40 to 125 c ? 0.5 a c in d input capacitance ? ? 10 pf 1. these specifications are design targets and subject to change per device characterization. 2. ?sr? parameter values must not exceed the absolute maximum ratings shown in table 9 .
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 electrical characteristics doc id 16100 rev 7 63/103 3.10.4 input dc electrical characteristics definition figure 14 shows the dc electrical characteristics behavior as function of time. figure 14. input dc electrical characteristics definition table 22. supply current (3.3 v, nvusro[pad3v5v] = 1) symbol c parameter conditions value (1) unit typ max i dd_lv_corx t supply current run?maximum mode (2) v dd_lv_corx externally forced at 1.3 v 40 mhz 44 55 ma 64 mhz 52 65 run?typical mode (3) 40 mhz 38 46 64 mhz 45 54 p halt mode (4) ?1.510 stop mode (5) ?110 i dd_adc tadc v dd_hv_adc0 at 3.3 v f adc =16mhz adc_0 3 4 i dd_osc t oscillator v dd_hv_osc at 3.3 v 8 mhz 2.6 3.2 i dd_hv_reg d internal regulator module current consumption v dd_hv_reg at 5.5 v ? 10 1. all values to be confirmed afte r characterization/data collection. 2. maximum mode: flexpwm, adc, ctu, dspi, linflex, flexcan, 15 output pins, pll_0 enabled, 125 c ambient. i/o supply current excluded. 3. typical mode configurations: dspi, linflex, flexcan, 15 output pins, pll_0, 105 c ambient. i/o supply current excluded. 4. halt mode configurations: code fetched from sram, code flash memory and data flash memory in low power mode, osc/pll_0 are off, core clock frozen, all peripherals disabled. 5. stop ?p? mode device under test (dut) configuration: code fetched from sram, code flash memory and data flash memory off, osc/pll_0 are off, core clock frozen, all peripherals disabled. v il v in v ih pdix = ?1? v dd v hys (gpdi register of siul) pdix = ?0?
electrical characteristics spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 64/103 doc id 16100 rev 7 3.10.5 i/o pad current specification the i/o pads are distributed across the i/o supply segment. each i/o supply segment is associated to a v dd /v ss supply pair as described in ta ble 23 . table 23. i/o supply segment package supply segment 12345 lqfp100 pin15?pin26 pin27?pin46 pin51?pin61 pin64?pin86 pin89?pin10 lqfp64 pin8?pin17 pin18?pin30 pin33?pin38 pin41?pin54 pin57?pin5 table 24. i/o consumption symbol c parameter conditions (1) value unit min typ max i swtslw (2) c c d dynamic i/o current for slow configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 ??20 ma v dd = 3.3 v 10%, pad3v5v = 1 ??16 i swtmed (2) c c d dynamic i/o current for medium configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 ??29 ma v dd = 3.3 v 10%, pad3v5v = 1 ??17 i swtfst (2) c c d dynamic i/o current for fast configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 ??110 ma v dd = 3.3 v 10%, pad3v5v = 1 ??50 i rmsslw c c d root medium square i/o current for slow configuration c l = 25 pf, 2 mhz v dd = 5.0 v 10%, pad3v5v = 0 ??2.3 ma c l = 25 pf, 4 mhz ? ? 3.2 c l = 100 pf, 2 mhz ? ? 6.6 c l = 25 pf, 2 mhz v dd = 3.3 v 10%, pad3v5v = 1 ??1.6 c l = 25 pf, 4 mhz ? ? 2.3 c l = 100 pf, 2 mhz ? ? 4.7 i rmsmed c c d root medium square i/o current for medium configuration c l = 25 pf, 13 mhz v dd = 5.0 v 10%, pad3v5v = 0 ??6.6 ma c l = 25 pf, 40 mhz ? ? 13.4 c l = 100 pf, 13 mhz ? ? 18.3 c l = 25 pf, 13 mhz v dd = 3.3 v 10%, pad3v5v = 1 ?? 5 c l = 25 pf, 40 mhz ? ? 8.5 c l = 100 pf, 13 mhz ? ? 11
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 electrical characteristics doc id 16100 rev 7 65/103 3.11 main oscillator electrical characteristics the spc560p34/spc560p40 provides an oscillator/resonator driver. i rmsfst c c d root medium square i/o current for fast configuration c l = 25 pf, 40 mhz v dd = 5.0 v 10%, pad3v5v = 0 ??22 ma c l = 25 pf, 64 mhz ? ? 33 c l = 100 pf, 40 mhz ? ? 56 c l = 25 pf, 40 mhz v dd = 3.3 v 10%, pad3v5v = 1 ??14 c l = 25 pf, 64 mhz ? ? 20 c l = 100 pf, 40 mhz ? ? 35 i avgseg s r d sum of all the static i/o current within a supply segment v dd = 5.0 v 10%, pad3v5v = 0 ? ? 70 ma v dd = 3.3 v 10%, pad3v5v = 1 ? ? 65 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ?40 to 125 c, unless otherwise specified 2. stated maximum values represent peak consumption that lasts only a few ns during i/o transition. table 24. i/o consumption (continued) symbol c parameter conditions (1) value unit min typ max table 25. main oscillator output electrical characteristics (5.0 v, nvusro[pad3v5v] = 0) symbol c parameter conditions value unit min max f osc sr ? oscillator frequency 4 40 mhz g m ? p transconductance 6.5 25 ma/v v osc ? t oscillation amplitude on xtal pin 1 ? v t oscsu ? t start-up time (1),(2) 1. the start-up time is dependent upon crystal characteristics, board leakage, etc. high esr and excessive capacitive loads can cause long start-up time. 2. value captured when amplitude reaches 90% of xtal 8?ms c l cc t xtal load capacitance (3) 3. this value is determined by the crystal manufacturer and board design. for 4 mhz to 40 mhz crystals specified for this oscillator, load c apacitors should not exceed these limits. 4mhz 5 30 pf t8mhz526 t12mhz523 t16mhz519 t20mhz516 t40mhz58
electrical characteristics spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 66/103 doc id 16100 rev 7 3.12 fmpll electrical characteristics table 26. main oscillator output electrical characteristics (3.3 v, nvusro[pad3v5v] = 1) symbol c parameter conditions value unit min max f osc sr ? oscillator frequency 4 40 mhz g m ? p transconductance 4 20 ma/v v osc ? t oscillation amplitude on xtal pin 1 ? v t oscsu ? t start-up time (1),(2) 1. the start-up time is dependent upon crystal characteristics, board leakage, etc. high esr and excessive capacitive loads can cause long start-up time. 2. value captured when amplitude reaches 90% of xtal 8?ms c l cc t xtal load capacitance (3) 3. this value is determined by the crystal manufacturer and board design. for 4 mhz to 40 mhz crystals specified for this oscillator, load c apacitors should not exceed these limits. 4mhz 5 30 pf t8mhz526 t12mhz523 t16mhz519 t20mhz516 t40mhz58 table 27. input clock characteristics symbol parameter value unit min typ max f osc sr oscillator frequency 4 ? 40 mhz f clk sr frequency in bypass ? ? 64 mhz t rclk sr rise/fall time in bypass ? ? 1 ns t dc sr duty cycle 47.5 50 52.5 % table 28. fmpll electrical characteristics symbol c parameter conditions (1) value unit min max f ref_crystal f ref_ext d pll reference frequency range (2) crystal reference 4 40 mhz f pllin d phase detector input frequency range (after pre-divider) ?416mhz f fmpllout d clock frequency range in normal mode ? 16 64 mhz
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 electrical characteristics doc id 16100 rev 7 67/103 f free p free-running frequency measured using clock division?typically /16 20 150 mhz t cyc d system clock period ? ? 1 / f sys ns f lorl d loss of reference frequency window (3) lower limit 1.6 3.7 mhz f lorh d upper limit 24 56 f scm d self-clocked mode frequency (4),(5) ?20150mhz c jitter t clkout period jitter (6),(7),(8),(9) short-term jitter (10) f sys maximum ? 44%f clkout long-term jitter (average over 2 ms interval) f pllin =16mhz (resonator), f pllclk at 64 mhz, 4000 cycles ?10 ns t lpll d pll lock time (11), (12) ??200s t dc d duty cycle of reference ? 40 60 % f lck d frequency lock range ? ? 66%f sys f ul d frequency un-lock range ? ? 18 18 % f sys f cs d modulation depth center spread 0.25 4.0 (13) %f sys f ds d down spread ? 0.5 ? 8.0 f mod d modulation frequency (14) ??70khz 1. v dd_lv_corx = 1.2 v 10%; v ss = 0 v; t a = ?40 to 125 c, unless otherwise specified 2. considering operation with pll not bypassed. 3. ?loss of reference frequency? window is the reference frequenc y range outside of which the pll is in self clocked mode. 4. self clocked mode frequency is the frequency that the pll operates at when the reference frequency falls outside the f lor window. 5. f vco self clock range is 20?150 mhz. f scm represents f sys after pll output divider (erfd) of 2 through 16 in enhanced mode. 6. this value is determined by the crystal manufacturer and board design. 7. jitter is the average deviation from the programmed frequency meas ured over the specified interval at maximum f sys . measurements are made with the device pow ered by filtered supplies and clocked by a stable external clock signal. noise injected into the pll circuitry via v dd_lv_cor0 and v ss_lv_cor0 and variation in crystal oscillator frequency increase the c jitter percentage for a given interval. 8. proper pc board layout procedures must be followed to achieve specifications. 9. values are obtained with frequency modulation disabled. if frequency modulation is enabled, jitter is the sum of c jitter and either f cs or f ds (depending on whether center spread or down spread modulation is enabled). 10. short term jitter is measured on the clock rising edge at cycle n and cycle n+4. 11. this value is determined by the crystal manufacturer and boar d design. for 4 mhz to 20 mhz crystals specified for this pll, load capacitors should not exceed these limits. 12. this specification applies to the period required for the p ll to relock after changing the mfd frequency control bits in the synthesizer control register (syncr). 13. this value is true when operating at frequencies above 60 mhz, otherwise f cs is 2% (above 64 mhz). 14. modulation depth will be attenuated from depth setting when operating at modulation frequencies above 50 khz. table 28. fmpll electrical characteristics (continued) symbol c parameter conditions (1) value unit min max
electrical characteristics spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 68/103 doc id 16100 rev 7 3.13 16 mhz rc oscillator electrical characteristics 3.14 analog-to-digital converter (adc) electrical characteristics the device provides a 10-bit successive approximation register (sar) analog-to-digital converter. figure 15. adc characteristics and error definitions table 29. 16 mhz rc oscillator electrical characteristics symbol c parameter conditions value unit min typ max f rc p rc oscillator frequency t a = 25 c ? 16 ? mhz rcmvar p fast internal rc oscillator variation over temperature and supply with respect to f rc at t a = 25 c in high-frequency configuration ? ? 5? 5% (2) (1) (3) (4) (5) offset error (e o ) offset error (e o ) gain error (e g ) 1 lsb (ideal) 1023 1022 1021 1020 1019 1018 5 4 3 2 1 0 7 6 1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023 (1) example of an actual transfer curve (2) the ideal transfer curve (3) differential non-linearity error (dnl) (4) integral non-linearity error (inl) (5) center of a step of the actual transfer curve 1 lsb ideal = v dd_adc / 1024 v in(a) (lsb ideal ) code out
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 electrical characteristics doc id 16100 rev 7 69/103 3.14.1 input impedance and adc accuracy to preserve the accuracy of the a/d converter, it is necessary that analog input pins have low ac impedance. placing a capacitor with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as possible, ideally infinite. this capacitor contributes to attenuating the noise present on the input pin; further, it sources charge during the sampling phase, when the analog signal source is a high- impedance source. a real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple rc filter). the rc filtering may be limited according to the source impedance value of the transducer or circuit supplying the analog signal to be measured. the filter at the input pins must be designed taking into account the dynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the adc itself. in fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: c s and c p2 being substantially two switched capacitances, with a frequency equal to the adc conversion rate, it can be seen as a resistive path to ground. for instance, assuming a conversion rate of 1 mhz, with c s +c p2 equal to 3 pf, a resistance of 330 k is obtained (r eq = 1 / (fc (c s +c p2 )), where fc represents the conversion rate at the considered channel). to minimize the error induced by the voltage partitioning between this resistance (sampled voltage on c s +c p2 ) and the sum of r s + r f , the external circuit must be designed to respect the equation 4 : equation 4 equation 4 generates a constraint for external network design, in particular on resistive path. v a r s r f + r eq --------------------- ? 1 2 -- -lsb <
electrical characteristics spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 70/103 doc id 16100 rev 7 figure 16. input equivalent circuit a second aspect involving the capacitance network shall be considered. assuming the three capacitances c f , c p1 and c p2 are initially charged at the source voltage v a (refer to the equivalent circuit reported in figure 16 ): a charge sharing phenomenon is installed when the sampling phase is started (a/d switch closed). figure 17. transient behavior during sampling phase r f c f r s r l r sw c p2 c s v dd sampling source filter current limiter external circuit internal circuit scheme c p1 r ad channel selection v a r s : source impedance r f : filter resistance c f : filter capacitance r l : current limiter resistance r sw : channel selection switch impedance r ad : sampling switch impedance c p : pin capacitance (two contributions, c p1 and c p2 ) c s : sampling capacitance v a v a1 v a2 t t s v cs voltage transient on c s v < 0.5 lsb 1 2 1 < (r sw + r ad ) c s << t s 2 = r l (c s + c p1 + c p2 )
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 electrical characteristics doc id 16100 rev 7 71/103 in particular two different transient periods can be distinguished: a first and quick charge transfer from the internal capacitance c p1 and c p2 to the sampling capacitance c s occurs (c s is supposed initially completely discharged): considering a worst case (since the time constant in reality would be faster) in which c p2 is reported in parallel to c p1 (call c p = c p1 + c p2 ), the two capacitances c p and c s are in series, and the time constant is equation 5 equation 5 can again be simplified considering only c s as an additional worst condition. in reality, the transient is faster, but the a/d converter circuitry has been designed to be robust also in the very worst case: the sampling time t s is always much longer than the internal time constant: equation 6 the charge of c p1 and c p2 is redistributed also on c s , determining a new value of the voltage v a1 on the capacitance according to equation 7 : equation 7 a second charge transfer involves also c f (that is typically bigger than the on-chip capacitance) through the resistance r l : again considering the worst case in which c p2 and c s were in parallel to c p1 (since the time constant in reality would be faster), the time constant is: equation 8 in this case, the time constant depends on the external circuit: in particular imposing that the transient is completed well before the end of sampling time t s , a constraints on r l sizing is obtained: equation 9 of course, r l shall be sized also according to the current limitation constraints, in combination with r s (source impedance) and r f (filter resistance). being c f definitively bigger than c p1 , c p2 and c s , then the final voltage v a2 (at the end of the charge transfer transient) will be much higher than v a1 . equation 10 must be respected (charge balance assuming now c s already charged at v a1 ): equation 10 1 r sw r ad + () = c p c s ? c p c s + --------------------- - ? 1 r sw r ad + () < c s t s ? ? v a1 c s c p1 c p2 ++ () ? v a c p1 c p2 + () ? = 2 r l < c s c p1 c p2 ++ () ? 8.5 2 ? 8.5 r l c s c p1 c p2 ++ () ? ? =t s < v a2 c s c p1 c p2 c f +++ () ? v a c f ? v a1 +c p1 c p2 +c s + () ? =
electrical characteristics spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 72/103 doc id 16100 rev 7 the two transients above are not influenced by the voltage source that, due to the presence of the r f c f filter, is not able to provide the extra charge to compensate the voltage drop on c s with respect to the ideal source v a ; the time constant r f c f of the filter is very high with respect to the sampling time (t s ). the filter is typically designed to act as anti-aliasing. figure 18. spectral representation of input signal calling f 0 the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, f f ), according to the nyquist theorem the conversion rate f c must be at least 2f 0 ; it means that the constant time of the filter is greater than or at least equal to twice the conversion period (t c ). again the conversion period t c is longer than the sampling time t s , which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a specific channel): in conclusion it is evident that the time constant of the filter r f c f is definitively much higher than the sampling time t s , so the charge level on c s cannot be modified by the analog signal source during the time in which the sampling switch is closed. the considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage drop on c s ; from the two charge balance equations above, it is simple to derive equation 11 between the ideal and real sampled voltage on c s : equation 11 from this formula, in the worst case (when v a is maximum, that is for instance 5 v), assuming to accept a maximum error of half a count, a constraint is evident on c f value: equation 12 f 0 f analog source bandwidth (v a ) f 0 f sampled signal spectrum (f c = conversion rate) f c f anti-aliasing filter (f f = rc filter pole) f f 2 f 0 f c (nyquist) f f = f 0 (anti-aliasing filtering condition) t c 2 r f c f (conversion rate vs. filter pole) noise v a v a2 ----------- - c p1 c p2 +c f + c p1 c p2 +c f c s ++ ------------------------------------------------------- - = c f 2048 c s ? >
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 electrical characteristics doc id 16100 rev 7 73/103 3.14.2 adc conversion characteristics table 30. adc conversion characteristics symbol c parameter conditions (1) value unit min typ max f ck s r ? adc clock frequency (depends on adc configuration) (the duty cycle depends on adc clock (2) frequency) ?3 (3) ?60mhz f s s r ? sampling frequency ? ? ? 1.53 mhz t s ? d sampling time (4) f adc = 20 mhz, inpsamp = 3 125 ? ? ns f adc = 9 mhz, inpsamp = 255 ? ? 28.2 s t c ? p conversion time (5) f adc = 20 mhz (6) , inpcmp = 1 0.65 0 ??s t adc_p u s r ? adc power-up delay (time needed for adc to settle exiting from software power down; pwdn bit = 0) ???1.5s c s (7) ? d adc input sampling capacitance ? ? ? 2.5 pf c p1 (7) ? d adc input pin capacitance 1 ? ? ? 3 pf c p2 (7) ? d adc input pin capacitance 2 ? ? ? 1 pf r sw (7) ? d internal resistance of analog source v dd_hv_adc0 = 5 v 10% ? ? 0.6 k v dd_hv_adc0 = 3.3 v 10% ? ? 3 k r ad (7) ? d internal resistance of analog source ? ? ? 2 k i inj ? t input current injection current injection on one adc input, different from the converted one. remains within tue specification ? 5? 5ma inl c c p integral non-linearity no overload ? 1.5 ? 1.5 lsb dnl c c p differential non-linearity no overload ? 1.0 ? 1.0 lsb e o c c t offset error ? ? 1 ? lsb e g c c t gain error ? ? 1 ? lsb tue c c p total unadjusted error without current injection ? ? 2.5 ? 2.5 lsb tue c c t total unadjusted error with current injection ? ? 3? 3lsb 1. v dd = 3.3 v to 3.6 v / 4.5 v to 5.5 v, t a = ? 40 c to t a max , unless otherwise specified and analog input voltage from v ss_hv_adc0 to v dd_hv_adc0 . 2. ad_clk clock is always half of the adc module input clock defined via the auxiliary clock divider for the adc. 3. when configured to allow 60 mhz adc, the minimum adc clock speed is 9 mhz, below which the precision is lost.
electrical characteristics spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 74/103 doc id 16100 rev 7 3.15 flash memory electrical characteristics 3.15.1 program/erase characteristics 4. during the sampling time the input capacitance c s can be charged/discharged by the ex ternal source. the internal resistance of the analog source must allow the capacitance to reach its final voltage level within t s . after the end of the sampling time t s , changes of the analog input voltage have no effect on the conversion result. values for the sample clock t s depend on programming. 5. this parameter includes the sampling time t s . 6. 20 mhz adc clock. specific prescaler is programm ed on mc_pll_clk to provide 20 mhz clock to the adc. 7. see figure 16 . table 31. program and erase specifications symbol c parameter value unit min typ (1) initial max (2) max (3) t wprogram p word program time for data flash memory (4) ? 30 70 500 s t dwprogram p double word program time for code flash memory (4) ? 22 50 500 s t bkprg p bank program (256 kb) (4)(5) ? 0.73 0.83 17.5 s p bank program (64 kb) (4)(5) ?0.491.24.1s t 16kpperase p 16 kb block pre-program and erase time for code flash memory ? 300 500 5000 ms 16 kb block pre-program and erase time for data flash memory ? 700 800 5000 t 32kpperase p 32 kb block pre-program and erase time ? 400 600 5000 ms t 128kpperase p 128 kb block pre-program and erase time ? 800 1300 7500 ms t esrt p program and erase specifications (6) 10 ? ? ? ms 1. typical program and erase times assume nominal supply valu es and operation at 25 c. a ll times are subject to change pending device characterization. 2. initial factory condition: < 100 program/erase cycles, 25 c, typical supply voltage. 3. the maximum program and erase times occur after the specif ied number of program/erase cycles. these maximum values are characterized but not guaranteed. 4. actual hardware programming times. th is does not include software overhead. 5. typical bank programming time assumes that all cells are progr ammed in a single pulse. in reality some cells will require more than one pulse, adding a small overhead to total bank programming time (see ?initial max? column). 6. time between erase suspend resu me and next erase suspend request.
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 electrical characteristics doc id 16100 rev 7 75/103 3.15.2 flash memory power supply dc characteristics ta ble 34 shows the power supply dc characteristics on external supply. table 32. flash memory module life symbol c parameter conditions value unit min typ p/e c number of program/erase cycles per block for 16 kb blocks over the operating temperature range (t j ) ? 100000 ? cycles p/e c number of program/erase cycles per block for 32 kb blocks over the operating temperature range (t j ) ? 10000 100000 cycles p/e c number of program/erase cycles per block for 128 kb blocks over the operating temperature range (t j ) ? 1000 100000 cycles retention c minimum data retention at 85 c average ambient temperature (1) blocks with 0?1000 p/e cycles 20 ? years blocks with 10000 p/e cycles 10 ? years blocks with 100000 p/e cycles 5 ? years 1. ambient temperature averaged over dur ation of application, not to exceed recommended product operating temperature range. table 33. flash memory read access timing symbol c parameter conditions (1) max value unit f max c maximum working frequency for code flash memory at given number of wait states in worst conditions 2 wait states 66 mhz 0 wait states 18 f max c maximum working frequency for data flash memory at given number of wait states in worst conditions 8 wait states 66 mhz 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified table 34. flash memory power supply dc electrical characteristics symbol c parameter conditions (1) value unit min typ max i flpw c c d sum of the current consumption on v dd_hv_iox and v dd_lv_corx during low-power mode code flash memory ? ? 900 a i fpwd c c d sum of the current consumption on v dd_hv_iox and v dd_lv_corx during power-down mode code flash memory ? ? 150 a data flash memory ? ? 150 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified.
electrical characteristics spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 76/103 doc id 16100 rev 7 3.15.3 start-up/switch-off timings 3.16 ac specifications 3.16.1 pad ac specifications table 35. start-up time/switch-off time symbol c parameter conditions (1) value unit min typ max t flarstexit c c t delay for flash module to exit reset mode code flash memory ??125 s t data flash memory ? ? 125 t flalpexit c c d delay for flash module to exit low-power mode code flash memory ??0.5 t flapdexit c c t delay for flash module to exit power-down mode code flash memory ??30 t data flash memory ? ? 30 t flalpentry c c d delay for flash module to enter low-power mode code flash memory ??0.5 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. table 36. output pin transition times symbol c parameter conditions (1) value unit min typ max t tr cc d output transition time output pin (2) slow configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 ??50 ns tc l = 50 pf ? ? 100 dc l = 100 pf ? ? 125 dc l = 25 pf v dd = 3.3 v 10%, pad3v5v = 1 ??40 tc l = 50 pf ? ? 50 dc l = 100 pf ? ? 75 t tr cc d output transition time output pin (2) medium configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 siul.pcrx.src = 1 ??10 ns tc l = 50 pf ? ? 20 dc l = 100 pf ? ? 40 dc l = 25 pf v dd = 3.3 v 10%, pad3v5v = 1 siul.pcrx.src = 1 ??12 tc l = 50 pf ? ? 25 dc l = 100 pf ? ? 40
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 electrical characteristics doc id 16100 rev 7 77/103 figure 19. pad output delay 3.17 ac timing characteristics 3.17.1 reset pin characteristics the spc560p34/spc560p40 implements a dedicated bidirectional reset pin. t tr cc d output transition time output pin (2) fast configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 siul.pcrx.src = 1 ?? 4 ns c l = 50 pf ? ? 6 c l = 100 pf ? ? 12 c l = 25 pf v dd = 3.3 v 10%, pad3v5v = 1 siul.pcrx.src = 1 ?? 4 c l = 50 pf ? ? 7 c l = 100 pf ? ? 12 t sym (3) cc t symmetric transition time, same drive strength between n and p transistor v dd = 5.0 v 10%, pad3v5v = 0 ? ? 4 ns v dd = 3.3 v 10%, pad3v5v = 1 ? ? 5 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 c to t a max , unless otherwise specified. 2. c l includes device and package capacitances (c pkg < 5 pf). 3. transition timing of both positive and negative slopes will differ maximum 50%. table 36. output pin transition times (continued) symbol c parameter conditions (1) value unit min typ max v dd_hv_iox /2 v oh v ol rising edge output delay falling edge output delay pad data input pad output
electrical characteristics spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 78/103 doc id 16100 rev 7 figure 20. start-up reset requirements figure 21. noise filtering on reset signal v il v dd device reset forced by v reset v ddmin v reset v ih device start-up phase t por v reset v il v ih v dd filtered by hysteresis filtered by lowpass filter w frst w nfrst hw_rst ?1? ?0? filtered by lowpass filter w frst unknown reset state device under hardware reset
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 electrical characteristics doc id 16100 rev 7 79/103 table 37. reset electrical characteristics symbol c parameter conditions (1) value (2) unit min typ max v ih s r p input high level cmos (schmitt trigger) ?0.65v dd ?v dd +0.4 v v il s r p input low level cmos (schmitt trigger) ? ? 0.4 ? 0.35v dd v v hys c c c input hysteresis cmos (schmitt trigger) ?0.1v dd ??v v ol c c poutput low level push pull, i ol = 2 ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) ? ? 0.1v dd v push pull, i ol = 1 ma, v dd = 5.0 v 10%, pad3v5v = 1 (3) ? ? 0.1v dd push pull, i ol = 1 ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) ?? 0.5 t tr c c d output transition time output pin (4) medium configuration c l = 25 pf, v dd = 5.0 v 10%, pad3v5v = 0 ?? 10 ns c l = 50 pf, v dd = 5.0 v 10%, pad3v5v = 0 ?? 20 c l = 100 pf, v dd = 5.0 v 10%, pad3v5v = 0 ?? 40 c l = 25 pf, v dd = 3.3 v 10%, pad3v5v = 1 ?? 12 c l = 50 pf, v dd = 3.3 v 10%, pad3v5v = 1 ?? 25 c l = 100 pf, v dd = 3.3 v 10%, pad3v5v = 1 ?? 40 w frst s r p reset input filtered pulse ???40ns w nfrst s r p reset input not filtered pulse ? 500 ? ? ns t por c c d maximum delay before internal reset is released after all v dd_hv reach nominal supply monotonic v dd_hv supply ramp ? ? 1 ms |i wpu | c c p weak pull-up current absolute value v dd = 3.3 v 10%, pad3v5v = 1 10 ? 150 a v dd = 5.0 v 10%, pad3v5v = 0 10 ? 150 v dd = 5.0 v 10%, pad3v5v = 1 (5) 10 ? 250 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified 2. all values need to be confir med during device validation. 3. this is a transient configuration during power-up, up to the end of reset phase2 (refer to rgm module section of device reference manual).
electrical characteristics spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 80/103 doc id 16100 rev 7 3.17.2 ieee 1149.1 interface timing figure 22. jtag test clock input timing 4. c l includes device and package capacitance (c pkg <5pf). 5. the configuration pad3v5 = 1 when v dd = 5 v is only transient configuration dur ing power-up. all pads but reset and nexus output (mdox, evto, mcko) are configured in input or in high impedance state. table 38. jtag pin ac electrical characteristics no . symbol c parameter conditions value unit min max 1t jcyc cc d tck cycle time ? 100 ? ns 2t jdc cc d tck clock pulse width (measured at v dd_hv_iox /2) ? 40 60 ns 3t tckrise cc d tck rise and fall times (40%?70%) ? ? 3 ns 4t tmss, t tdis cc d tms, tdi data setup time ? 5 ? ns 5 t tmsh, t tdih cc d tms, tdi data hold time ? 25 ? ns 6t tdov cc d tck low to tdo data valid ? ? 40 ns 7t tdoi cc d tck low to tdo data invalid ? 0 ? ns 8t tdohz cc d tck low to tdo high impedance ? 40 ? ns 9t bsdv cc d tck falling edge to output valid ? ? 50 ns 10 t bsdvz cc d tck falling edge to output valid out of high impedance ? ? 50 ns 11 t bsdhz cc d tck falling edge to output high impedance ? ? 50 ns 12 t bsdst cc d boundary scan input valid to tck rising edge ? 50 ? ns 13 t bsdht cc d tck rising edge to boundary scan input invalid ? 50 ? ns tck 1 2 2 3 3
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 electrical characteristics doc id 16100 rev 7 81/103 figure 23. jtag test access port timing tck 4 5 6 7 8 tms, tdi tdo
electrical characteristics spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 82/103 doc id 16100 rev 7 figure 24. jtag boundary scan timing 3.17.3 nexus timing tck output signals input signals output signals 11 12 13 14 15 table 39. nexus debug port timing (1) no. symbol c parameter value unit min typ max 1t tcyc cc d tck cycle time 4 (2) ??t cyc 2 t ntdis cc d tdi data setup time 5 ? ? ns t ntmss cc d tms data setup time 5 ? ? ns 3 t ntdih cc d tdi data hold time 25 ? ? ns t ntmsh cc d tms data hold time 25 ? ? ns 4t tdov cc d tck low to tdo data valid 10 ? 20 ns 5t tdoi cc d tck low to tdo data invalid ? ? ? ns 1. all nexus timing relative to mcko is measured from 50% of mcko and 50% of the respective signal. 2. lower frequency is required to be fully compliant to standard.
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 electrical characteristics doc id 16100 rev 7 83/103 figure 25. nexus output timing figure 26. nexus event trigger and test clock timing 1 3 4 mcko mdo mseo evto output data valid 2 tck 5 evti evto
electrical characteristics spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 84/103 doc id 16100 rev 7 figure 27. nexus tdi, tms, tdo timing 3.17.4 external interrupt timing (irq pin) tdo 6 7 tms, tdi 8 tck 9 table 40. external interrupt timing (1) no. symbol c parameter conditions value unit min max 1t ipwl cc d irq pulse width low ? 4 ? t cyc 2t ipwh cc d irq pulse width high ? 4 ? t cyc 3t icyc cc d irq edge to edge time (2) ? 4+n (3) ?t cyc 1. irq timing specified at f sys = 64 mhz and v dd_hv_iox = 3.0 v to 5.5 v, t a =t l to t h , and c l = 200 pf with src = 0b00 2. applies when irq pins are configured for rising edge or falling edge events, but not both. 3. n = isr time to clear the flag
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 electrical characteristics doc id 16100 rev 7 85/103 figure 28. external interrupt timing 3.17.5 dspi timing irq 2 3 1 table 41. dspi timing (1) no. symbol c parameter conditions value unit min max 1t sck cc d dspi cycle time master (mtfe = 0) 60 ? ns slave (mtfe = 0) 60 ? 2t csc cc d cs to sck delay ? 16 ? ns 3t asc cc d after sck delay ? 26 ? ns 4t sdc cc d sck duty cycle ? 0.4 * t sck 0.6 * t sck ns 5t a cc d slave access time ss active to sout valid ? 30 ns 6t dis cc d slave sout disable time ss inactive to sout high impedance or invalid ? 16 ns 7t pcsc cc d pcsx to pcss time ? 13 ? ns 8t pasc cc d pcss to pcsx time ? 13 ? ns 9t sui cc d data setup time for inputs master (mtfe = 0) 35 ? ns slave 4? master (mtfe = 1, cpha = 0) 35 ? master (mtfe = 1, cpha = 1) 35 ? 10 t hi cc d data hold time for inputs master (mtfe = 0) ? 5 ? ns slave 4 ? master (mtfe = 1, cpha = 0) 11 ? master (mtfe = 1, cpha = 1) ? 5?
electrical characteristics spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 86/103 doc id 16100 rev 7 figure 29. dspi classic spi timing ? master, cpha = 0 11 t suo cc d data valid (after sck edge) master (mtfe = 0) ? 12 ns slave ? 36 master (mtfe = 1, cpha = 0) ?12 master (mtfe = 1, cpha = 1) ?12 12 t ho cc d data hold time for outputs master (mtfe = 0) ? 2? ns slave 6 ? master (mtfe = 1, cpha = 0) 6 ? master (mtfe = 1, cpha = 1) ? 2? 1. all timing are provided with 50 pf capacitanc e on output, 1 ns transition time on input signal table 41. dspi timing (1) (continued) no. symbol c parameter conditions value unit min max data last data first data first data data last data sin sout pcsx sck output 4 9 12 1 11 10 4 sck output (cpol=0) (cpol=1) 3 2 note : numbers shown reference table 41 .
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 electrical characteristics doc id 16100 rev 7 87/103 figure 30. dspi classic spi timing ? master, cpha = 1 figure 31. dspi classic spi timing ? slave, cpha = 0 data last data first data sin sout 12 11 10 last data data first data sck output sck output pcsx 9 (cpol=0) (cpol=1) note : numbers shown reference table 41 . last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 12 sck input first data last data sck input 2 (cpol=0) (cpol=1) note : numbers shown reference table 41 .
electrical characteristics spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 88/103 doc id 16100 rev 7 figure 32. dspi classic spi timing ? slave, cpha = 1 figure 33. dspi modified transfer format timing ? master, cpha = 0 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol=0) (cpol=1) note : numbers shown reference table 41 . pcsx 3 1 4 10 4 9 12 11 sck output sck output sin sout first data data last data first data data last data 2 (cpol=0) (cpol=1) note : numbers shown reference table 41 .
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 electrical characteristics doc id 16100 rev 7 89/103 figure 34. dspi modified transfer format timing ? master, cpha = 1 figure 35. dspi modified transfer format timing ? slave, cpha = 0 pcsx 10 9 12 11 sck output sck output sin sout first data data last data first data data last data (cpol=0) (cpol=1) note : numbers shown reference table 41 . last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 sck input first data last data sck input 2 (cpol=0) (cpol=1) 12 note : numbers shown reference table 41 .
electrical characteristics spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 90/103 doc id 16100 rev 7 figure 36. dspi modified transfer format timing ? slave, cpha = 1 figure 37. dspi pcs strobe (pcss ) timing 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol=0) (cpol=1) note : numbers shown reference table 41 . pcsx 7 8 pcss note : numbers shown reference table 41 .
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 package characteristics doc id 16100 rev 7 91/103 4 package characteristics 4.1 ecopack ? in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
package characteristics spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 92/103 doc id 16100 rev 7 4.2 package mechanical data 4.2.1 lqfp100 mechanical outline drawing figure 38. lqfp100 package mechanical drawing d d1 d3 75 51 50 76 100 26 125 e3 e1 e e b pin 1 identification seating plane gage plane c a a2 a1 c ccc 0.25 mm 0.10 inch l l1 k c 1l_me
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 package characteristics doc id 16100 rev 7 93/103 table 42. lqfp100 package mechanical data symbol dimensions mm inches (1) min typ max min typ max a ? ? 1.600 ? ? 0.0630 a1 0.050 ? 0.150 0.0020 ? 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 ? 0.200 0.0035 ? 0.0079 d 15.800 16.000 16.200 0.6220 0.6299 0.6378 d1 13.800 14.000 14.200 0.5433 0.5512 0.5591 d3 ? 12.000 ? ? 0.4724 ? e 15.800 16.000 16.200 0.6220 0.6299 0.6378 e1 13.800 14.000 14.200 0.5433 0.5512 0.5591 e3 ? 12.000 ? ? 0.4724 ? e ? 0.500 ? ? 0.0197 ? l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 ? 1.000 ? ? 0.0394 ? k 0.0 3.5 7.0 0.0 3.5 7.0 ccc (2) 0.08 0.0031 1. values in inches are converted from mil limeters (mm) and rounded to four decimal digits. 2. tolerance
package characteristics spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 94/103 doc id 16100 rev 7 4.2.2 lqfp64 mechanical outline drawing figure 39. lqfp64 package mechanical drawing 5w_me l a1 k l1 c a a2 ccc c d d1 d3 e3 e1 e 32 33 48 49 b 64 1 pin 1 identification 16 17 table 43. lqfp64 package mechanical data symbol dimensions mm inches (1) min typ max min typ max a??1.6??0.063 a1 0.05 ? 0.15 0.002 ? 0.0059 a2 1.35 1.4 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 ? 0.2 0.0035 ? 0.0079 d 11.8 12 12.2 0.4646 0.4724 0.4803 d1 9.8 10 10.2 0.3858 0.3937 0.4016 d3 ? 7.5 ? ? 0.2953 ? e 11.8 12 12.2 0.4646 0.4724 0.4803 e1 9.8 10 10.2 0.3858 0.3937 0.4016 e3 ? 7.5 ? ? 0.2953 ? e ? 0.5 ? ? 0.0197 ? l 0.45 0.6 0.75 0.0177 0.0236 0.0295 l1 ? 1 ? ? 0.0394 ?
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 package characteristics doc id 16100 rev 7 95/103 k 0.0 3.5 7.0 0.0 3.5 7.0 ccc (2) 0.08 0.0031 1. values in inches are converted from mil limeters (mm) and rounded to four decimal digits. 2. tolerance table 43. lqfp64 package mechanical data (continued) symbol dimensions mm inches (1) min typ max min typ max
ordering information spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 96/103 doc id 16100 rev 7 5 ordering information figure 40. commercial product code structure memory packing core family y = tray r = tape and reel x = tape and reel 90 a = 64 mhz, 5 v b = 64 mhz, 3.3 v c = 40 mhz, 5 v d = 40 mhz, 3.3 v f = full-featured a = airbag e = data flash 0 = no data flash b = ?40 to 105 c c = ?40 to 125 c l1 = lqfp64 l3 = lqfp100 34 = 192 kb 40 = 256 kb p = spc560px family 0 = e200z0 spc56 = power architecture in 90 nm temperature package custom vers. spc56 40 y 0p c l3 e f a example code: product identifier
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 ordering information doc id 16100 rev 7 97/103 appendix a abbreviations ta ble 44 lists abbreviations used in this document. table 44. abbreviations abbreviation meaning cmos complementary metal?oxide?semiconductor cpha clock phase cpol clock polarity cs peripheral chip select dut device under test ecc error code correction evto event out gpio general purpose input / output mc modulus counter mcko message clock out mcu microcontroller unit mdo message data out mseo message start/end out mtfe modified timing format enable npn negative-positive-negative nvusro non-volatile user options register ptf post trimming frequency pwm pulse width modulation risc reduced instruction set computer sck serial communications clock sout serial data out tbc to be confirmed tbd to be defined tck test clock input tdi test data input tdo test data output tms test mode select
revision history spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 98/103 doc id 16100 rev 7 revision history table 45. document revision history date revision changes 01-sep-2009 1 initial release. 21-may-2010 2 editorial updates updated the following items in the ?spc560p34/spc560p40 device comparison? table: ? the heading ? the ?sram? row ? the ?flexcan? row ? the ?ctu? row ? the ?flexpwm? row ? the ?linflex? row ? the ?dspi? row ? the ?nexus? row updated the ?spc560p34/spc560p40 device configuration difference? table: ? editorial updates ? added the ?ctu? row ? deleted the ?temperature? row ? swapped the content of airbag and full featured cells added the ?wakeup unit? block in the spc560p34/spc560p40 block diagram updated the ?absolute maximum ratings? table updated the ?recommended operating conditions (5.0 v)? table updated the ?recommended operating conditions (3.3 v)? table updated the ?thermal characteristics for 100-pin lqfp? table: ? jt : changed the typical value updated the ?emi testing specifications? table: replaced all values in ?level (max)? column with tbd updated the ?electrical characteristics? section: ? added the ?introduction? section ? added the ?parameter classification? section ? added the ?nvusro register? section ? added the ?power supplies constraints (?0.3 v v dd_hv_iox 6.0 v)? figure ? added the ?independent adc supply (?0.3 v v dd_hv_reg 6.0 v)? figure ? added the ?power supplies constraints (3.0 v v dd_hv_iox 5.5 v)? figure ? added the ?independent adc supply (3.0 v v dd_hv_reg 5.5 v)? figure updated the ?power management electrical characteristics? section updated the ?power up/down sequencing? section updated the ?dc electrical characteristics? section ? deleted the ?nvusro register? section ? updated the ?dc electrical characteristics (5.0 v, nvusro[pad3v5v] = 0)? section: ? deleted all rows concerning reset ? deleted ?i vpp ? row ? added the max value for c in
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 revision history doc id 16100 rev 7 99/103 21-may-2010 2 (continued) ? updated the ?dc electrical characteristics (3.3 v, nvusro[pad3v5v] = 0)? section: ? deleted all rows concerning reset ? deleted ?i vpp ? row ? added the max value for c in added the ?i/o pad current specification? section updated the order codes table. added ?appendix a? 23-dec-2010 3 ?introduction? section: ? changed title (was ?overview?) ? updated contents ?spc560p34/spc560p40 device comparison? table: ? added sentence above table ? removed ?flexray? row ? ?flexcan? row: removed link to footnote 2 for spc560p34 ? updated ?safety port? row for spc560p34 ? updated ?dspi? row for spc560p34 ?spc560p34/spc560p40 block diagram?: added the following blocks: mc_cgm, mc_me, mc_pcu, mc_rgm, crc, and sscm added ?spc560p34/spc560p40 series block summary? table ?pin muxing? section: removed information on ?symmetric pads? ?electrical characteristics? section: ? updated ?caution? note ? demoted ?nvusro register? section to subsection of ?dc electrical characteristics? section ? ?nvusro register? section: deleted ?nvusro[watchdog_en] field description? section updated ?emi testing specifications? table ?low voltage monitor electrical characteristics? table: updated v mlvddok_h max value ?dc electrical characteristics (5.0 v, nvusro[pad3v5v] = 0)? table: removed vol_sym , and v oh_sym rows ?supply current (5.0 v, nvusro[pad3v5v] = 0)? table: ?i dd_lv_core , run?maximum mode, 40/64 mhz: updated typ/max values ?i dd_lv_core , run?airbag mode, 40/64 mhz: updated typ/max values ?i dd_lv_core , run?maximum mode, ?p? parameter classification: removed ?i dd_flash : removed rows ?i dd_adc , maximum mode: updated typ/max values ?i dd_osc : updated max value updated ?dc electrical characteristics (3.3 v, nvusro[pad3v5v] = 1)? table ?supply current (3.3 v, nvusro[pad3v5v] = 1)? table: ?i dd_lv_core , run?maximum mode, 40/64 mhz: updated typ/max values ?i dd_lv_core , run?airbag mode, 40/64 mhz: updated typ/max values ?i dd_flash : removed rows ?i dd_adc , maximum mode: updated typ/max values ?i dd_osc : updated max value added ?i/o consumption? table removed ?i/o weight? table table 45. document revision history (continued) date revision changes
revision history spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 100/103 doc id 16100 rev 7 23-dec-2010 3 (continued) updated ?main oscillator electrical characteristics (5.0 v, nvusro[pad3v5v] = 0)? table updated ?main oscillator electrical characteristics (3.3 v, nvusro[pad3v5v] = 1)? table ?input clock characteristics? table: updated f clk max value ?pllmrfm electrical specifications (v ddpll = 1.08 v to 1.32 v, v ss = v sspll = 0 v, t a =t l to t h )? table: ? updated supply voltage range for v ddpll in the table title ? updated f scm max value ? updated c jitter row ? updated f mod max value updated ?16 mhz rc oscillator electrical characteristics? table updated ?adc conversion characteristics? table ?program and erase specifications? table: ?t wprogram : updated initial max and max values ?t bkprg , 64 kb: updated initial max and max values ? added information about ?erase time? for data flash ?flash module life? table: ? p/e, 32 kb: added typ value ? p/e, 128 kb: added typ value replaced ?pad ac specifications (5.0 v, nvusro[pad3v5v] = 0)? and ?pad ac specifications (3.3 v, invusro[pad3v5v] = 1)? tables with ?output pin transition times? table ?jtag pin ac electrical characteristics? table: ?t tdov : updated max value ?t tdohz : added min value and removed max value ?nexus debug port timing? table: removed the rows ?t mcyc ?, ?t mdov ?, ?t mseov ?, and ?t evtov ? updated ?external interrupt timing (irq pin)? table updated ?flexcan timing? table updated ?dspi timing? table updated ?ordering information? section table 45. document revision history (continued) date revision changes
spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 revision history doc id 16100 rev 7 101/103 13-may-2011 4 editorial and formatting changes throughout cover page features list: ? changed core feature ?64 mhz? to ?up to 64 mhz? ? changed data flash memory ?64 (4 16) kb? to ?additional 64 (4 16) kb? ? changed ?1 flexcan interface? to ?up to 2 flexcan interface? updated device summary section ?introduction?: reorganized contents spc560p40 device configuration differences: editorial changes to indicate that the table concerns only the spc560p40 devices); removed ?dspi? row block diagram (spc560p40 full-featured configuration): reorganized blocks above and below peripheral bridge; made arrow going from peripheral bridge to crossbar switch bidirectional; removed spc560p34 part number from title added section ?features details? 64-pin and 100-pin lqfp pinout diagrams: replaced instances of hv_ad0 with hv_adc0 system pins: updated ?xtal? and ?extal? rows updated lqfp thermal characteristics updated emi testing specifications section ?voltage regulator electrical characteristics?: removed bcp56 from named bjts; replaced two configuration diagrams and two electrical characteristics tables with single diagram and single table voltage regulator electrical characteristics: updated v dd_lv_regcor row low voltage monitor electrical characteristics: updated v mlvddok_h max value?was 1.15 v; is 1.145 v supply current (5.0 v, nvusro[pad3v5v] = 0): changed symbol i dd_lv_core to i dd_lv_corx ; changed parameter classification from t to p for i dd_lv_corx run? maximum mode at 64 mhz; added i dd_flash characteristics; replaced instances of ?airbag? mode with ?typical mode? supply current (3.3 v, nvusro[pad3v5v] = 1): changed symbol i dd_lv_core to i dd_lv_corx ; replaced instances of ?airbag? mode with ?typical mode? dc electrical characteristics (3.3 v, nvusro[pad3v5v] = 1): corrected parameter description for v ol_f ?was ?fast, high level output voltage?; is ?fast, low level output voltage? added section 3.10.4, input dc electrical characteristics definition main oscillator output electrical characteristics tables: replaced instances of extal with xtal; added load capacitance parameter fmpll electrical characteristics: updated conditions and table title; removed f sys row; updated f fmpllout values; replaced instances of v ddpll with v dd_lv_cor0 ; replaced instances of v sspll with v ss_lv_cor0 16 mhz rc oscillator electrical characteristics: removed rows rcmtrim and rcmstep adc characteristics and error definitions: updated symbols adc conversion characteristics: updated symbols; added row t adc_pu added section 3.15.2, flash memory power supply dc characteristics added section 3.15.3, start-up/switch-off timings removed section ?generic timing diagrams? updated start-up reset requirements diagram removed flexcan timing characteristics reset electrical characteristics: added row for t por in the range of figures ?dspi classic spi timing ? master, cpha = 0? to ?dspi pcs strobe (pcss) timing?: added note updated order codes table 45. document revision history (continued) date revision changes
revision history spc560p34l1, spc560p34l3, SPC560P40L1, spc560p40l3 102/103 doc id 16100 rev 7 13-may-2011 4 (continued) commercial product code structure: replaced ?conditioning? with ?packing? table 44 : added ?dut?, ?npn?, and ?risc? 22-dec-2011 5 updated table 1: device summary updated section 1.5.28: nexus development interface (ndi) section table 2.: spc560p34/spc560p40 device comparison : changed nexus l1+ with nexus class 1 table 7: pin muxing : removed e[0] row table 9: absolute maximum ratings : updated minumum and maximum values for tv dd parameter section 3.10: dc electrical characteristics : removed oscillator margin. removed section nvusro[oscillator_margin] field description and table nvusro[oscillator_margin] field description updated section 3.8.1: voltage regulator electrical characteristics updated section figure 10.: voltage regulator configuration table 16: voltage regulator electrical characteristics : added l reg row, updated condition for c dec1 , c dec2 and c dec3 removed ?order codes? tables 20-dec-2012 6 table 9 (absolute maximum ratings) : updated tv dd parameter, the minimum value to 3.0 v/s, added note on minimum value, and the maximum value to 0.5 v/s table 20 (supply current (5.0 v, nvusro[pad3v5v] = 0)) : added i dd_hv_reg row table 22 (supply current (3.3 v, nvusro[pad3v5v] = 1)) : added i dd_hv_reg row updated section 3.14.1, input impedance and adc accuracy table 30 (adc conversion characteristics) : renamed ?r sw1 ? in ?r sw ? table 31 (program and erase specifications) : added t esrt row 18-sep-2013 7 updated disclaimer. table 45. document revision history (continued) date revision changes
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